Synopsys Generic Technology Mapper, Version mapact, Build 976R, Built May 23 2013 12:46:43
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version H-2013.03M-1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)

@W:MO171 : phase_check.vhd(54) | Sequential instance trigger_receiver_0.phase_check.phase_checker.sclkR reduced to a combinational gate by constant propagation 
@W:MO171 : posdge_pulse.vhd(37) | Sequential instance RCU_DEC_0.U6_ABSCNT.U3_TRSFPULSEA.dff_out1 reduced to a combinational gate by constant propagation 
@W:MO171 : posdge_pulse.vhd(37) | Sequential instance RCU_DEC_0.U6_ABSCNT.U4_TRSFPULSEB.dff_out1 reduced to a combinational gate by constant propagation 
@W:MO171 : posdge_pulse.vhd(37) | Sequential instance RCU_DEC_0.U6_ABSCNT.U5_ACKPULSEA.dff_out1 reduced to a combinational gate by constant propagation 
@W:MO171 : posdge_pulse.vhd(37) | Sequential instance RCU_DEC_0.U6_ABSCNT.U6_ACKPULSEB.dff_out1 reduced to a combinational gate by constant propagation 
@W:MO171 : posdge_pulse.vhd(37) | Sequential instance RCU_DEC_0.U6_ABSCNT.U7_CSTBPULSEA.dff_out1 reduced to a combinational gate by constant propagation 
@W:MO171 : posdge_pulse.vhd(37) | Sequential instance RCU_DEC_0.U6_ABSCNT.U8_CSTBPULSEB.dff_out1 reduced to a combinational gate by constant propagation 
@N:BN362 : arbit.vhd(44) | Removing sequential instance pr_st[0:2] of view:PrimLib.statemachine(prim) in hierarchy view:work.ARBIT(a_arbit) because there are no references to its outputs 
@N:BN115 : rcu_dec.vhd(562) | Removing instance RCU_DEC_0.U2_ARBIT of view:work.ARBIT(a_arbit) because there are no references to its outputs 
@W:BN132 : rcu_dec.vhd(729) | Removing sequential instance RCU_DEC_0.blk_err_reg,  because it is equivalent to instance RCU_DEC_0.add_err_reg
@W:BN132 : rcu_dec.vhd(516) | Removing sequential instance RCU_DEC_0.scel_err_reg[5],  because it is equivalent to instance RCU_DEC_0.add_err_reg
@W:BN132 : abs_cnt.vhd(200) | Removing user instance RCU_DEC_0.U6_ABSCNT.U8_CSTBCNTB,  because it is equivalent to instance RCU_DEC_0.U6_ABSCNT.U7_CSTBCNTA
@W:BN132 : abs_cnt.vhd(185) | Removing user instance RCU_DEC_0.U6_ABSCNT.U7_CSTBCNTA,  because it is equivalent to instance RCU_DEC_0.U6_ABSCNT.U6_ACKCNTB
@W:BN132 : abs_cnt.vhd(169) | Removing user instance RCU_DEC_0.U6_ABSCNT.U6_ACKCNTB,  because it is equivalent to instance RCU_DEC_0.U6_ABSCNT.U5_ACKCNTA
@W:BN132 : abs_cnt.vhd(139) | Removing user instance RCU_DEC_0.U6_ABSCNT.U4_TRSFCNTB,  because it is equivalent to instance RCU_DEC_0.U6_ABSCNT.U5_ACKCNTA
@W:BN132 : abs_cnt.vhd(124) | Removing user instance RCU_DEC_0.U6_ABSCNT.U3_TRSFCNTA,  because it is equivalent to instance RCU_DEC_0.U6_ABSCNT.U5_ACKCNTA
@W:BN132 : abs_cnt.vhd(109) | Removing user instance RCU_DEC_0.U6_ABSCNT.U2_DSTBCNTB,  because it is equivalent to instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA

Available hyper_sources - for debug and ip models
	None Found

@W:MT462 : hp_cdr.vhd(64) | Net ttc_0.cdr_top.cdr.clk_out appears to be an unidentified clock source. Assuming default frequency. 
@W:MT462 : hp_cdr.vhd(63) | Net ttc_0.cdr_top.cdr.input_d appears to be an unidentified clock source. Assuming default frequency. 
@W:BN132 : rcu_dec.vhd(743) | Removing sequential instance RCU_DEC_0.chadd_err_cnt_r[11:0],  because it is equivalent to instance RCU_DEC_0.bl_err_cnt_r[11:0]

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 139MB)

@W:BN132 : rcu_dec.vhd(527) | Removing instance RCU_DEC_0.scel_err_reg[0],  because it is equivalent to instance RCU_DEC_0.add_err_reg
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[0] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[1] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[2] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[3] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[4] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[5] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[6] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[7] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[8] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[9] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[10] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[11] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[12] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[13] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[14] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[15] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[16] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[17] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[18] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[19] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[20] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[21] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[22] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[23] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[24] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[25] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[26] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[27] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[28] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[29] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[30] reduced to a combinational gate by constant propagation
@W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[31] reduced to a combinational gate by constant propagation
@N:BN362 : rcu_dec.vhd(527) | Removing sequential instance RCU_DEC_0.scel_err_reg[1] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : rcu_dec.vhd(527) | Removing sequential instance RCU_DEC_0.scel_err_reg[2] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : rcu_dec.vhd(527) | Removing sequential instance RCU_DEC_0.scel_err_reg[3] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : rcu_dec.vhd(527) | Removing sequential instance RCU_DEC_0.scel_err_reg[4] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : rcu_dec.vhd(743) | Removing sequential instance RCU_DEC_0.add_err_reg in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
Encoding state machine current_state[0:3] (view:work.apb_to_dcs(arc))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@W:MO129 : apb_to_dcs.vhd(98) | Sequential instance apb_to_dcs_0.current_state[0] reduced to a combinational gate by constant propagation
@N:BN362 : cmd_decoder.vhd(53) | Removing sequential instance cmd_vector[7] of view:PrimLib.dffr(prim) in hierarchy view:work.CMD_DECODER(a_cmddecoder) because there are no references to its outputs 
@N:BN362 : cmd_decoder.vhd(53) | Removing sequential instance cmd_vector[0] of view:PrimLib.dffr(prim) in hierarchy view:work.CMD_DECODER(a_cmddecoder) because there are no references to its outputs 
@N:BN362 : cmd_decoder.vhd(53) | Removing sequential instance cmd_vector[1] of view:PrimLib.dffr(prim) in hierarchy view:work.CMD_DECODER(a_cmddecoder) because there are no references to its outputs 
@N:BN362 : cmd_decoder.vhd(53) | Removing sequential instance cmd_vector[2] of view:PrimLib.dffr(prim) in hierarchy view:work.CMD_DECODER(a_cmddecoder) because there are no references to its outputs 
@N:BN362 : cmd_decoder.vhd(53) | Removing sequential instance cmd_vector[3] of view:PrimLib.dffr(prim) in hierarchy view:work.CMD_DECODER(a_cmddecoder) because there are no references to its outputs 
@N:BN362 : cmd_decoder.vhd(53) | Removing sequential instance cmd_vector[6] of view:PrimLib.dffr(prim) in hierarchy view:work.CMD_DECODER(a_cmddecoder) because there are no references to its outputs 
@N:BN362 : rcu_reg.vhd(212) | Removing sequential instance rdrx_reg in hierarchy view:work.RCU_REG(a_rcureg) because there are no references to its outputs 
@N: : cnt20.vhd(38) | Found counter in view:work.CNT20(a_cnt20) inst cnt[19:0]
@W:MO160 : cnt12.vhd(37) | Register bit cnt[11] is always 0, optimizing ...
@W:MO160 : cnt12.vhd(37) | Register bit cnt[10] is always 0, optimizing ...
@W:MO160 : cnt12.vhd(37) | Register bit cnt[9] is always 0, optimizing ...
@W:MO160 : cnt12.vhd(37) | Register bit cnt[8] is always 0, optimizing ...
@W:MO160 : cnt12.vhd(37) | Register bit cnt[7] is always 0, optimizing ...
@W:MO160 : cnt12.vhd(37) | Register bit cnt[6] is always 0, optimizing ...
@W:MO160 : cnt12.vhd(37) | Register bit cnt[5] is always 0, optimizing ...
@W:MO160 : cnt12.vhd(37) | Register bit cnt[4] is always 0, optimizing ...
@W:MO160 : cnt12.vhd(37) | Register bit cnt[3] is always 0, optimizing ...
@W:MO160 : cnt12.vhd(37) | Register bit cnt[2] is always 0, optimizing ...
@W:MO160 : cnt12.vhd(37) | Register bit cnt[1] is always 0, optimizing ...
@W:MO160 : cnt12.vhd(37) | Register bit cnt[0] is always 0, optimizing ...
Encoding state machine current_state[0:6] (view:work.serialb_com(behave))
original code -> new code
   0000001 -> 0000001
   0000010 -> 0000010
   0000100 -> 0000100
   0001000 -> 0001000
   0010000 -> 0010000
   0100000 -> 0100000
   1000000 -> 1000000
@N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L1_message_reg_0[0] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs 
@N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L1_message_reg_0[1] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs 
@N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L1_message_reg_0[2] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs 
@N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L1_message_reg_0[3] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs 
@N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L1_message_reg_0[11] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs 
@N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L2a_message_reg_3[2] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs 
@N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L2a_message_reg_3[3] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs 
@N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L2a_message_reg_3[4] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs 
@N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L2a_message_reg_3[5] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs 
@N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L2a_message_reg_3[6] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs 
@N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L2a_message_reg_3[7] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs 
@N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L2a_message_reg_3[11] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs 
@W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L1_state[1],  because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L1_state[0]
@W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L1_state[2],  because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L1_state[0]
@W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L1_state[3],  because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L1_state[0]
@W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L1_state[4],  because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L1_state[0]
@W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L1_state[5],  because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L1_state[0]
@W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L1_state[6],  because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L1_state[0]
@W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L1_state[7],  because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L1_state[0]
@W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L1_state[12],  because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L1_state[0]
@W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L2_state[8],  because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L2_state[0]
@W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L2_state[9],  because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L2_state[0]
@W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L2_state[10],  because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L2_state[0]
@W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L2_state[11],  because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L2_state[0]
@W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L2_state[12],  because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L2_state[0]
@N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L1_state[0] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs 
@N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L2_state[0] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs 
Encoding state machine current_state[0:8] (view:work.sequence_validator(behave))
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
@N: : phase_check.vhd(61) | Found counter in view:work.phase_check(behave) inst phase_cnt[4:0]
@N: : fifocore_sync_scntr.vhd(216) | Found updn counter in view:work.fifo_wrapper(behave) inst microsemi_version\.CDH_fifo.ms_event_fifo_0.CFIFOl10\.CFIFOi10.CFIFOlOOi[7:0] 
@N: : fifocore_sync_scntr.vhd(315) | Found counter in view:work.fifo_wrapper(behave) inst microsemi_version\.CDH_fifo.ms_event_fifo_0.CFIFOl10\.CFIFOi10.CFIFOI0ol[6:0]
@N: : fifocore_sync_scntr.vhd(305) | Found counter in view:work.fifo_wrapper(behave) inst microsemi_version\.CDH_fifo.ms_event_fifo_0.CFIFOl10\.CFIFOi10.CFIFOl0OL[6:0]
@N: : counters.vhd(188) | Found counter in view:work.counters(arc) inst pp_Counter_i[15:0]
@N: : counters.vhd(188) | Found counter in view:work.counters(arc) inst L2r_Counter_i[15:0]
@N: : counters.vhd(188) | Found counter in view:work.counters(arc) inst L2a_Counter_i[15:0]
@N: : counters.vhd(188) | Found counter in view:work.counters(arc) inst L1_msg_Counter_i[15:0]
@N: : counters.vhd(188) | Found counter in view:work.counters(arc) inst L1_Counter_i[15:0]
@N: : counters.vhd(188) | Found counter in view:work.counters(arc) inst L0_Counter_i[15:0]
@N: : counters.vhd(142) | Found counter in view:work.counters(arc) inst seqErrorCnt_i[15:0]
@N: : counters.vhd(142) | Found counter in view:work.counters(arc) inst sbError_Count[15:0]
@N: : counters.vhd(142) | Found counter in view:work.counters(arc) inst msgErrorCnt_i[15:0]
@N: : counters.vhd(142) | Found counter in view:work.counters(arc) inst dbError_Count[15:0]
@N: : counters.vhd(169) | Found counter in view:work.counters(arc) inst Bunch_Counter_i[12:0]
@N:FX404 : counters.vhd(255) | Found addmux in view:work.counters(arc) inst p_BCID_local\.BCID_Local_i_6[11:0] from un1_Bunch_Counter_i_1[12:1] 
@N:MF179 : counters.vhd(298) | Found 16 bit by 16 bit '==' comparator, 'p_timewindow\.un29_tw_counter'
@N:MF179 : counters.vhd(305) | Found 16 bit by 16 bit '==' comparator, 'p_timewindow\.un37_tw_counter'
@N:MF179 : counters.vhd(309) | Found 16 bit by 16 bit '==' comparator, 'p_timewindow\.un39_tw_counter'
@N:MF179 : counters.vhd(312) | Found 16 bit by 16 bit '==' comparator, 'p_timewindow\.un42_tw_counter'
@N:MF179 : counters.vhd(316) | Found 16 bit by 16 bit '==' comparator, 'p_timewindow\.un44_tw_counter'
@N:MF179 : counters.vhd(319) | Found 16 bit by 16 bit '==' comparator, 'p_timewindow\.un46_tw_counter'
@N:BN362 : addressed_msg_decoder.vhd(127) | Removing sequential instance addressed_message_decoder.current_state[0] in hierarchy view:work.trigger_receiver(arc) because there are no references to its outputs 
@N:BN362 : cmd_decoder.vhd(53) | Removing sequential instance RCU_DEC_0.U4_CMDDECODER.cmd_vector[5] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 

Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 156MB peak: 157MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 158MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 158MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 158MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 159MB peak: 159MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 158MB peak: 159MB)

@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[0] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[1] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[2] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[3] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[4] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[5] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[6] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[7] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[8] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[9] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[10] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[11] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[12] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[13] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[14] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[15] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[16] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[17] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[18] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[19] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 
@N:BN362 : cmd_decoder.vhd(53) | Removing sequential instance RCU_DEC_0.U4_CMDDECODER.cmd_vector[4] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs 

Finished preparing to map (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 158MB peak: 159MB)


Finished technology mapping (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 224MB peak: 227MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:08s		   -16.09ns		1927 /       840
   2		0h:00m:08s		   -15.41ns		1927 /       840
------------------------------------------------------------

@N:FX271 : sequence_validator.vhd(261) | Instance "trigger_receiver_0.Sequence_validator.busy" with 21 loads replicated 2 times to improve timing 
@N:FX271 : addressed_msg_decoder.vhd(298) | Instance "trigger_receiver_0.addressed_message_decoder.receiving_L2a_i" with 4 loads replicated 1 times to improve timing 
@N:FX271 : addressed_msg_decoder.vhd(298) | Instance "trigger_receiver_0.addressed_message_decoder.receiving_L1_i" with 9 loads replicated 1 times to improve timing 
@N:FX271 : sequence_validator.vhd(261) | Instance "trigger_receiver_0.Sequence_validator.init_sequence" with 9 loads replicated 1 times to improve timing 
Timing driven replication report
Added 5 Registers via timing driven replication
Added 3 LUTs via timing driven replication

@N:FX271 : addressed_msg_decoder.vhd(298) | Instance "trigger_receiver_0.addressed_message_decoder.receiving_L2r_i" with 4 loads replicated 1 times to improve timing 
Timing driven replication report
Added 1 Registers via timing driven replication
Added 1 LUTs via timing driven replication

@N:FX271 : rcu_com_release.vhd(127) | Instance "trigger_receiver_0.RCU_bus_communication.L1_Latency_reg[0]" with 5 loads replicated 1 times to improve timing 
@N:FX271 : counters.vhd(220) | Instance "trigger_receiver_0.Counters.L1R" with 4 loads replicated 1 times to improve timing 
@N:FX271 : rcu_com_release.vhd(127) | Instance "trigger_receiver_0.RCU_bus_communication.module_reset" with 44 loads replicated 2 times to improve timing 
Timing driven replication report
Added 4 Registers via timing driven replication
Added 2 LUTs via timing driven replication

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:08s		   -13.59ns		1932 /       850
------------------------------------------------------------



Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:08s		   -13.59ns		1932 /       850
------------------------------------------------------------

@N:FP130 :  | Promoting Net ttc_0.clk_div.change_ph_3_i on CLKINT  I_200  
@N:FP130 :  | Promoting Net Trigger_receiver_v1_7_MSS_0_MSS_RESET_N_M2F on CLKINT  I_201  
@N:FP130 :  | Promoting Net trigger_receiver_0.N_120_i_0 on CLKINT  I_202  

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 169MB peak: 227MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 170MB peak: 227MB)



#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
1 non-gated/non-generated clock tree(s) driving 835 clock pin(s) of sequential element(s)
3 gated/generated clock tree(s) driving 16 clock pin(s) of sequential element(s)
0 instances converted, 16 sequential instances remain driven by gated/generated clocks

========================================= Non-Gated/Non-Generated Clocks =========================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                           
------------------------------------------------------------------------------------------------------------------
ClockId0004       FCCC_1.GL0_INST     CLKINT                 835        Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST
==================================================================================================================
============================================================================================================= Gated/Generated Clocks ==============================================================================================================
Clock Tree ID     Driving Element               Drive Element Type     Fanout     Sample Instance                    Explanation                                                                                                                   
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0001       ttc_0.clk_div.change_ph_3     SLE                    9          ttc_0.ch_b_det.count[4]            No generated or derived clock directive on output of sequential instance                                                      
ClockId0002       ttc_0.cdr_top.cdr.clk_out     CFG2                   6          ttc_0.cdr_top.cdr.data_out         Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements
ClockId0003       ttc_0.cdr_top.cdr.input_d     CFG2                   1          ttc_0.cdr_top.cdr.output_e_del     Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements
===================================================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]

Writing Analyst data base C:\Microsemi\Projects\Trigger_receiver_v1_7\synthesis\Trigger_receiver_v1_7.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 166MB peak: 227MB)

Writing EDIF Netlist and constraint files
H-2013.03M-1 

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 167MB peak: 227MB)

@W:MT246 : trigger_receiver_v1_7.vhd(748) | Blackbox SYSRESET is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : ms_event_fifo_ms_event_fifo_0_usram_top.vhd(284) | Blackbox RAM64x18 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : trigger_receiver_v1_7_fccc_1_fccc.vhd(109) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT420 :  | Found inferred clock clk_div|change_ph_3_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:ttc_0.clk_div.change_ph_3" 

@W:MT420 :  | Found inferred clock Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FCCC_1.GL0_net" 



##### START OF TIMING REPORT #####[
# Timing Report written on Fri Oct 18 11:54:05 2013
#


Top view:               Trigger_receiver_v1_7
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing. 

@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock. 



Performance Summary 
*******************


Worst slack in design: -1.035

                                                             Requested     Estimated     Requested     Estimated                Clock        Clock              
Starting Clock                                               Frequency     Frequency     Period        Period        Slack      Type         Group              
----------------------------------------------------------------------------------------------------------------------------------------------------------------
Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     100.0 MHz     90.6 MHz      10.000        11.035        -1.035     inferred     Inferred_clkgroup_1
clk_div|change_ph_3_inferred_clock                           100.0 MHz     322.4 MHz     10.000        3.102         3.972      inferred     Inferred_clkgroup_0
System                                                       100.0 MHz     359.4 MHz     10.000        2.783         7.217      system       system_clkgroup    
================================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                                              |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                                  Ending                                                    |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                                    System                                                    |  10.000      7.217   |  No paths    -      |  No paths    -      |  No paths    -    
System                                                    clk_div|change_ph_3_inferred_clock                        |  10.000      6.948   |  No paths    -      |  10.000      8.868  |  No paths    -    
clk_div|change_ph_3_inferred_clock                        System                                                    |  10.000      8.534   |  No paths    -      |  No paths    -      |  No paths    -    
clk_div|change_ph_3_inferred_clock                        clk_div|change_ph_3_inferred_clock                        |  10.000      6.898   |  No paths    -      |  No paths    -      |  5.000       3.972
clk_div|change_ph_3_inferred_clock                        Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock  |  No paths    -       |  No paths    -      |  Diff grp    -      |  No paths    -    
Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock  System                                                    |  10.000      2.422   |  No paths    -      |  No paths    -      |  No paths    -    
Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock  Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock  |  10.000      -1.035  |  10.000      8.800  |  5.000       3.642  |  5.000       3.362
===========================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                         Starting                                                                                            Arrival           
Instance                                                 Reference                                                    Type     Pin     Net                   Time        Slack 
                                                         Clock                                                                                                                 
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
trigger_receiver_0.serialb_decoder.received_word[18]     Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      Q       received_data[18]     0.108       -1.035
trigger_receiver_0.serialb_decoder.received_word[23]     Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      Q       received_data[23]     0.108       -0.948
trigger_receiver_0.serialb_decoder.received_word[25]     Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      Q       received_data[25]     0.108       -0.923
trigger_receiver_0.serialb_decoder.received_word[21]     Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      Q       received_data[21]     0.108       -0.923
trigger_receiver_0.serialb_decoder.received_word[19]     Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      Q       received_data[19]     0.108       -0.901
trigger_receiver_0.serialb_decoder.received_word[17]     Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      Q       received_data[17]     0.108       -0.884
trigger_receiver_0.serialb_decoder.received_word[13]     Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      Q       received_data[13]     0.108       -0.863
trigger_receiver_0.serialb_decoder.received_word[15]     Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      Q       received_data[15]     0.108       -0.760
trigger_receiver_0.serialb_decoder.received_word[34]     Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      Q       received_data[34]     0.108       -0.729
trigger_receiver_0.serialb_decoder.received_word[14]     Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      Q       received_data[14]     0.108       -0.710
===============================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                      Starting                                                                                                         Required           
Instance                                                              Reference                                                    Type     Pin     Net                                Time         Slack 
                                                                      Clock                                                                                                                               
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
trigger_receiver_0.addressed_message_decoder.current_state[8]         Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      D       N_169_i_0                          9.745        -1.035
trigger_receiver_0.addressed_message_decoder.current_state[9]         Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      D       N_168_i_0                          9.745        -1.035
trigger_receiver_0.addressed_message_decoder.current_state[10]        Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      D       N_11_i_0                           9.745        -1.035
trigger_receiver_0.addressed_message_decoder.current_state[7]         Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      D       N_17_i_0                           9.745        -0.836
trigger_receiver_0.addressed_message_decoder.current_state[2]         Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      D       current_state_3[2]                 9.745        -0.645
trigger_receiver_0.addressed_message_decoder.msg_error                Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      D       msg_error_7                        9.745        -0.355
trigger_receiver_0.addressed_message_decoder.current_state[3]         Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      D       current_state_3[3]                 9.745        -0.338
trigger_receiver_0.addressed_message_decoder.current_state[4]         Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      D       current_state_3[4]                 9.745        -0.338
trigger_receiver_0.addressed_message_decoder.L2a_message_reg_2[0]     Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      EN      L2a_message_reg_2_1_sqmuxa_i_0     9.662        -0.299
trigger_receiver_0.addressed_message_decoder.L2a_message_reg_2[1]     Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     SLE      EN      L2a_message_reg_2_1_sqmuxa_i_0     9.662        -0.299
==========================================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.255
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.745

    - Propagation time:                      10.780
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.035

    Number of logic level(s):                9
    Starting point:                          trigger_receiver_0.serialb_decoder.received_word[18] / Q
    Ending point:                            trigger_receiver_0.addressed_message_decoder.current_state[8] / D
    The start point is clocked by            Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock [rising] on pin CLK

Instance / Net                                                                                       Pin      Pin               Arrival     No. of    
Name                                                                                        Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------
trigger_receiver_0.serialb_decoder.received_word[18]                                        SLE      Q        Out     0.108     0.108       -         
received_data[18]                                                                           Net      -        -       0.897     -           8         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_7_1[6]                              CFG4     D        In      -         1.006       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_7_1[6]                              CFG4     Y        Out     0.472     1.478       -         
syndrom_adrdata_0_a2_7_1[6]                                                                 Net      -        -       0.715     -           4         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_3[1]                                CFG4     B        In      -         2.193       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_3[1]                                CFG4     Y        Out     0.165     2.358       -         
syndrom_adrdata_0_a2_3[1]                                                                   Net      -        -       0.715     -           4         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2[1]                                  CFG2     A        In      -         3.073       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2[1]                                  CFG2     Y        Out     0.103     3.176       -         
syndrom_adrdata[1]                                                                          Net      -        -       1.000     -           24        
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_RNI8K6V[0]                          CFG4     D        In      -         4.176       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_RNI8K6V[0]                          CFG4     Y        Out     0.470     4.646       -         
adrdata_m2_i_o2_a0_1                                                                        Net      -        -       0.678     -           3         
trigger_receiver_0.hamming_decoder.adrdata_out_14_sqmuxa_3_RNI79K91                         CFG4     D        In      -         5.324       -         
trigger_receiver_0.hamming_decoder.adrdata_out_14_sqmuxa_3_RNI79K91                         CFG4     Y        Out     0.472     5.797       -         
adrdata_N_7_i                                                                               Net      -        -       0.993     -           23        
trigger_receiver_0.addressed_message_decoder.p_decoder\.un29_adrdata_ready                  CFG4     D        In      -         6.790       -         
trigger_receiver_0.addressed_message_decoder.p_decoder\.un29_adrdata_ready                  CFG4     Y        Out     0.470     7.259       -         
un29_adrdata_ready                                                                          Net      -        -       1.200     -           70        
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2_0[11]     CFG2     A        In      -         8.459       -         
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2_0[11]     CFG2     Y        Out     0.103     8.562       -         
N_51                                                                                        Net      -        -       0.678     -           3         
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2[10]       CFG4     D        In      -         9.241       -         
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2[10]       CFG4     Y        Out     0.472     9.713       -         
N_77                                                                                        Net      -        -       0.678     -           3         
trigger_receiver_0.addressed_message_decoder.current_state_RNO[8]                           CFG4     C        In      -         10.392      -         
trigger_receiver_0.addressed_message_decoder.current_state_RNO[8]                           CFG4     Y        Out     0.230     10.621      -         
N_169_i_0                                                                                   Net      -        -       0.159     -           1         
trigger_receiver_0.addressed_message_decoder.current_state[8]                               SLE      D        In      -         10.780      -         
======================================================================================================================================================
Total path delay (propagation time + setup) of 11.035 is 3.321(30.1%) logic and 7.714(69.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      10.000
    - Setup time:                            0.255
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.745

    - Propagation time:                      10.780
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.035

    Number of logic level(s):                9
    Starting point:                          trigger_receiver_0.serialb_decoder.received_word[18] / Q
    Ending point:                            trigger_receiver_0.addressed_message_decoder.current_state[10] / D
    The start point is clocked by            Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock [rising] on pin CLK

Instance / Net                                                                                       Pin      Pin               Arrival     No. of    
Name                                                                                        Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------
trigger_receiver_0.serialb_decoder.received_word[18]                                        SLE      Q        Out     0.108     0.108       -         
received_data[18]                                                                           Net      -        -       0.897     -           8         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_7_1[6]                              CFG4     D        In      -         1.006       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_7_1[6]                              CFG4     Y        Out     0.472     1.478       -         
syndrom_adrdata_0_a2_7_1[6]                                                                 Net      -        -       0.715     -           4         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_3[1]                                CFG4     B        In      -         2.193       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_3[1]                                CFG4     Y        Out     0.165     2.358       -         
syndrom_adrdata_0_a2_3[1]                                                                   Net      -        -       0.715     -           4         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2[1]                                  CFG2     A        In      -         3.073       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2[1]                                  CFG2     Y        Out     0.103     3.176       -         
syndrom_adrdata[1]                                                                          Net      -        -       1.000     -           24        
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_RNI8K6V[0]                          CFG4     D        In      -         4.176       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_RNI8K6V[0]                          CFG4     Y        Out     0.470     4.646       -         
adrdata_m2_i_o2_a0_1                                                                        Net      -        -       0.678     -           3         
trigger_receiver_0.hamming_decoder.adrdata_out_14_sqmuxa_3_RNI79K91                         CFG4     D        In      -         5.324       -         
trigger_receiver_0.hamming_decoder.adrdata_out_14_sqmuxa_3_RNI79K91                         CFG4     Y        Out     0.472     5.797       -         
adrdata_N_7_i                                                                               Net      -        -       0.993     -           23        
trigger_receiver_0.addressed_message_decoder.p_decoder\.un29_adrdata_ready                  CFG4     D        In      -         6.790       -         
trigger_receiver_0.addressed_message_decoder.p_decoder\.un29_adrdata_ready                  CFG4     Y        Out     0.470     7.259       -         
un29_adrdata_ready                                                                          Net      -        -       1.200     -           70        
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2_0[11]     CFG2     A        In      -         8.459       -         
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2_0[11]     CFG2     Y        Out     0.103     8.562       -         
N_51                                                                                        Net      -        -       0.678     -           3         
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2[10]       CFG4     D        In      -         9.241       -         
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2[10]       CFG4     Y        Out     0.472     9.713       -         
N_77                                                                                        Net      -        -       0.678     -           3         
trigger_receiver_0.addressed_message_decoder.current_state_RNO[10]                          CFG4     C        In      -         10.392      -         
trigger_receiver_0.addressed_message_decoder.current_state_RNO[10]                          CFG4     Y        Out     0.230     10.621      -         
N_11_i_0                                                                                    Net      -        -       0.159     -           1         
trigger_receiver_0.addressed_message_decoder.current_state[10]                              SLE      D        In      -         10.780      -         
======================================================================================================================================================
Total path delay (propagation time + setup) of 11.035 is 3.321(30.1%) logic and 7.714(69.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      10.000
    - Setup time:                            0.255
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.745

    - Propagation time:                      10.780
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.035

    Number of logic level(s):                9
    Starting point:                          trigger_receiver_0.serialb_decoder.received_word[18] / Q
    Ending point:                            trigger_receiver_0.addressed_message_decoder.current_state[9] / D
    The start point is clocked by            Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock [rising] on pin CLK

Instance / Net                                                                                       Pin      Pin               Arrival     No. of    
Name                                                                                        Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------
trigger_receiver_0.serialb_decoder.received_word[18]                                        SLE      Q        Out     0.108     0.108       -         
received_data[18]                                                                           Net      -        -       0.897     -           8         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_7_1[6]                              CFG4     D        In      -         1.006       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_7_1[6]                              CFG4     Y        Out     0.472     1.478       -         
syndrom_adrdata_0_a2_7_1[6]                                                                 Net      -        -       0.715     -           4         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_3[1]                                CFG4     B        In      -         2.193       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_3[1]                                CFG4     Y        Out     0.165     2.358       -         
syndrom_adrdata_0_a2_3[1]                                                                   Net      -        -       0.715     -           4         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2[1]                                  CFG2     A        In      -         3.073       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2[1]                                  CFG2     Y        Out     0.103     3.176       -         
syndrom_adrdata[1]                                                                          Net      -        -       1.000     -           24        
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_RNI8K6V[0]                          CFG4     D        In      -         4.176       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_RNI8K6V[0]                          CFG4     Y        Out     0.470     4.646       -         
adrdata_m2_i_o2_a0_1                                                                        Net      -        -       0.678     -           3         
trigger_receiver_0.hamming_decoder.adrdata_out_14_sqmuxa_3_RNI79K91                         CFG4     D        In      -         5.324       -         
trigger_receiver_0.hamming_decoder.adrdata_out_14_sqmuxa_3_RNI79K91                         CFG4     Y        Out     0.472     5.797       -         
adrdata_N_7_i                                                                               Net      -        -       0.993     -           23        
trigger_receiver_0.addressed_message_decoder.p_decoder\.un29_adrdata_ready                  CFG4     D        In      -         6.790       -         
trigger_receiver_0.addressed_message_decoder.p_decoder\.un29_adrdata_ready                  CFG4     Y        Out     0.470     7.259       -         
un29_adrdata_ready                                                                          Net      -        -       1.200     -           70        
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2_0[11]     CFG2     A        In      -         8.459       -         
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2_0[11]     CFG2     Y        Out     0.103     8.562       -         
N_51                                                                                        Net      -        -       0.678     -           3         
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2[10]       CFG4     D        In      -         9.241       -         
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2[10]       CFG4     Y        Out     0.472     9.713       -         
N_77                                                                                        Net      -        -       0.678     -           3         
trigger_receiver_0.addressed_message_decoder.current_state_RNO[9]                           CFG4     C        In      -         10.392      -         
trigger_receiver_0.addressed_message_decoder.current_state_RNO[9]                           CFG4     Y        Out     0.230     10.621      -         
N_168_i_0                                                                                   Net      -        -       0.159     -           1         
trigger_receiver_0.addressed_message_decoder.current_state[9]                               SLE      D        In      -         10.780      -         
======================================================================================================================================================
Total path delay (propagation time + setup) of 11.035 is 3.321(30.1%) logic and 7.714(69.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      10.000
    - Setup time:                            0.255
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.745

    - Propagation time:                      10.692
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.948

    Number of logic level(s):                9
    Starting point:                          trigger_receiver_0.serialb_decoder.received_word[23] / Q
    Ending point:                            trigger_receiver_0.addressed_message_decoder.current_state[8] / D
    The start point is clocked by            Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock [rising] on pin CLK

Instance / Net                                                                                       Pin      Pin               Arrival     No. of    
Name                                                                                        Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------
trigger_receiver_0.serialb_decoder.received_word[23]                                        SLE      Q        Out     0.108     0.108       -         
received_data[23]                                                                           Net      -        -       0.778     -           4         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_0[5]                                CFG2     B        In      -         0.886       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_0[5]                                CFG2     Y        Out     0.165     1.051       -         
N_130                                                                                       Net      -        -       0.630     -           2         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_9[6]                                CFG4     D        In      -         1.681       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_9[6]                                CFG4     Y        Out     0.472     2.153       -         
N_152                                                                                       Net      -        -       0.770     -           6         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2[1]                                  CFG2     B        In      -         2.923       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2[1]                                  CFG2     Y        Out     0.165     3.088       -         
syndrom_adrdata[1]                                                                          Net      -        -       1.000     -           24        
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_RNI8K6V[0]                          CFG4     D        In      -         4.088       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_RNI8K6V[0]                          CFG4     Y        Out     0.470     4.558       -         
adrdata_m2_i_o2_a0_1                                                                        Net      -        -       0.678     -           3         
trigger_receiver_0.hamming_decoder.adrdata_out_14_sqmuxa_3_RNI79K91                         CFG4     D        In      -         5.236       -         
trigger_receiver_0.hamming_decoder.adrdata_out_14_sqmuxa_3_RNI79K91                         CFG4     Y        Out     0.472     5.709       -         
adrdata_N_7_i                                                                               Net      -        -       0.993     -           23        
trigger_receiver_0.addressed_message_decoder.p_decoder\.un29_adrdata_ready                  CFG4     D        In      -         6.702       -         
trigger_receiver_0.addressed_message_decoder.p_decoder\.un29_adrdata_ready                  CFG4     Y        Out     0.470     7.172       -         
un29_adrdata_ready                                                                          Net      -        -       1.200     -           70        
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2_0[11]     CFG2     A        In      -         8.372       -         
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2_0[11]     CFG2     Y        Out     0.103     8.475       -         
N_51                                                                                        Net      -        -       0.678     -           3         
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2[10]       CFG4     D        In      -         9.153       -         
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2[10]       CFG4     Y        Out     0.472     9.626       -         
N_77                                                                                        Net      -        -       0.678     -           3         
trigger_receiver_0.addressed_message_decoder.current_state_RNO[8]                           CFG4     C        In      -         10.304      -         
trigger_receiver_0.addressed_message_decoder.current_state_RNO[8]                           CFG4     Y        Out     0.230     10.534      -         
N_169_i_0                                                                                   Net      -        -       0.159     -           1         
trigger_receiver_0.addressed_message_decoder.current_state[8]                               SLE      D        In      -         10.692      -         
======================================================================================================================================================
Total path delay (propagation time + setup) of 10.948 is 3.382(30.9%) logic and 7.565(69.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      10.000
    - Setup time:                            0.255
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.745

    - Propagation time:                      10.692
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.948

    Number of logic level(s):                9
    Starting point:                          trigger_receiver_0.serialb_decoder.received_word[23] / Q
    Ending point:                            trigger_receiver_0.addressed_message_decoder.current_state[10] / D
    The start point is clocked by            Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock [rising] on pin CLK
    The end   point is clocked by            Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock [rising] on pin CLK

Instance / Net                                                                                       Pin      Pin               Arrival     No. of    
Name                                                                                        Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------------
trigger_receiver_0.serialb_decoder.received_word[23]                                        SLE      Q        Out     0.108     0.108       -         
received_data[23]                                                                           Net      -        -       0.778     -           4         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_0[5]                                CFG2     B        In      -         0.886       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_0[5]                                CFG2     Y        Out     0.165     1.051       -         
N_130                                                                                       Net      -        -       0.630     -           2         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_9[6]                                CFG4     D        In      -         1.681       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_9[6]                                CFG4     Y        Out     0.472     2.153       -         
N_152                                                                                       Net      -        -       0.770     -           6         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2[1]                                  CFG2     B        In      -         2.923       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2[1]                                  CFG2     Y        Out     0.165     3.088       -         
syndrom_adrdata[1]                                                                          Net      -        -       1.000     -           24        
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_RNI8K6V[0]                          CFG4     D        In      -         4.088       -         
trigger_receiver_0.hamming_decoder.syndrom_adrdata_0_a2_RNI8K6V[0]                          CFG4     Y        Out     0.470     4.558       -         
adrdata_m2_i_o2_a0_1                                                                        Net      -        -       0.678     -           3         
trigger_receiver_0.hamming_decoder.adrdata_out_14_sqmuxa_3_RNI79K91                         CFG4     D        In      -         5.236       -         
trigger_receiver_0.hamming_decoder.adrdata_out_14_sqmuxa_3_RNI79K91                         CFG4     Y        Out     0.472     5.709       -         
adrdata_N_7_i                                                                               Net      -        -       0.993     -           23        
trigger_receiver_0.addressed_message_decoder.p_decoder\.un29_adrdata_ready                  CFG4     D        In      -         6.702       -         
trigger_receiver_0.addressed_message_decoder.p_decoder\.un29_adrdata_ready                  CFG4     Y        Out     0.470     7.172       -         
un29_adrdata_ready                                                                          Net      -        -       1.200     -           70        
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2_0[11]     CFG2     A        In      -         8.372       -         
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2_0[11]     CFG2     Y        Out     0.103     8.475       -         
N_51                                                                                        Net      -        -       0.678     -           3         
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2[10]       CFG4     D        In      -         9.153       -         
trigger_receiver_0.addressed_message_decoder.p_state_driver\.current_state_3_i_o2[10]       CFG4     Y        Out     0.472     9.626       -         
N_77                                                                                        Net      -        -       0.678     -           3         
trigger_receiver_0.addressed_message_decoder.current_state_RNO[10]                          CFG4     C        In      -         10.304      -         
trigger_receiver_0.addressed_message_decoder.current_state_RNO[10]                          CFG4     Y        Out     0.230     10.534      -         
N_11_i_0                                                                                    Net      -        -       0.159     -           1         
trigger_receiver_0.addressed_message_decoder.current_state[10]                              SLE      D        In      -         10.692      -         
======================================================================================================================================================
Total path delay (propagation time + setup) of 10.948 is 3.382(30.9%) logic and 7.565(69.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: clk_div|change_ph_3_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                      Starting                                                                    Arrival          
Instance                              Reference                              Type     Pin     Net                 Time        Slack
                                      Clock                                                                                        
-----------------------------------------------------------------------------------------------------------------------------------
ttc_0.demultiplexAB.data_80_delay     clk_div|change_ph_3_inferred_clock     SLE      Q       data_80_delay       0.087       3.972
ttc_0.demultiplexAB.ch_a              clk_div|change_ph_3_inferred_clock     SLE      Q       ch_a_c              0.108       6.898
ttc_0.ch_b_det.count[1]               clk_div|change_ph_3_inferred_clock     SLE      Q       count[1]            0.108       7.779
ttc_0.ch_b_det.count[2]               clk_div|change_ph_3_inferred_clock     SLE      Q       count[2]            0.108       7.827
ttc_0.ch_b_det.count[0]               clk_div|change_ph_3_inferred_clock     SLE      Q       count[0]            0.108       7.856
ttc_0.ch_b_det.count[3]               clk_div|change_ph_3_inferred_clock     SLE      Q       count[3]            0.108       8.272
ttc_0.ch_b_det.ch_b_det               clk_div|change_ph_3_inferred_clock     SLE      Q       ch_b_detected_c     0.087       8.534
ttc_0.ch_b_det.count[4]               clk_div|change_ph_3_inferred_clock     SLE      Q       count[4]            0.108       8.573
===================================================================================================================================


Ending Points with Worst Slack
******************************

                             Starting                                                                  Required          
Instance                     Reference                              Type     Pin     Net               Time         Slack
                             Clock                                                                                       
-------------------------------------------------------------------------------------------------------------------------
ttc_0.demultiplexAB.ch_b     clk_div|change_ph_3_inferred_clock     SLE      D       data_80_delay     4.745        3.972
ttc_0.ch_b_det.count[0]      clk_div|change_ph_3_inferred_clock     SLE      SLn     N_1519_i          9.662        6.898
ttc_0.ch_b_det.count[1]      clk_div|change_ph_3_inferred_clock     SLE      SLn     N_1519_i          9.662        6.898
ttc_0.ch_b_det.count[2]      clk_div|change_ph_3_inferred_clock     SLE      SLn     N_1519_i          9.662        6.898
ttc_0.ch_b_det.count[3]      clk_div|change_ph_3_inferred_clock     SLE      SLn     N_1519_i          9.662        6.898
ttc_0.ch_b_det.count[4]      clk_div|change_ph_3_inferred_clock     SLE      SLn     N_1519_i          9.662        6.898
ttc_0.ch_b_det.count[0]      clk_div|change_ph_3_inferred_clock     SLE      EN      count_or[4]       9.662        6.935
ttc_0.ch_b_det.count[1]      clk_div|change_ph_3_inferred_clock     SLE      EN      count_or[4]       9.662        6.935
ttc_0.ch_b_det.count[2]      clk_div|change_ph_3_inferred_clock     SLE      EN      count_or[4]       9.662        6.935
ttc_0.ch_b_det.count[3]      clk_div|change_ph_3_inferred_clock     SLE      EN      count_or[4]       9.662        6.935
=========================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      5.000
    - Setup time:                            0.255
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.745

    - Propagation time:                      0.773
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 3.972

    Number of logic level(s):                0
    Starting point:                          ttc_0.demultiplexAB.data_80_delay / Q
    Ending point:                            ttc_0.demultiplexAB.ch_b / D
    The start point is clocked by            clk_div|change_ph_3_inferred_clock [falling] on pin CLK
    The end   point is clocked by            clk_div|change_ph_3_inferred_clock [rising] on pin CLK

Instance / Net                                 Pin      Pin               Arrival     No. of    
Name                                  Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------
ttc_0.demultiplexAB.data_80_delay     SLE      Q        Out     0.087     0.087       -         
data_80_delay                         Net      -        -       0.685     -           1         
ttc_0.demultiplexAB.ch_b              SLE      D        In      -         0.773       -         
================================================================================================
Total path delay (propagation time + setup) of 1.028 is 0.343(33.3%) logic and 0.685(66.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                               Starting                                                                                                  Arrival          
Instance                       Reference     Type               Pin                  Net                                                 Time        Slack
                               Clock                                                                                                                      
----------------------------------------------------------------------------------------------------------------------------------------------------------
SYSRESET_0                     System        SYSRESET           POWER_ON_RESET_N     SYSRESET_0_POWER_ON_RESET_N                         0.000       6.948
FCCC_0.CCC_INST                System        CCC                GL2                  GL2_net                                             0.000       7.217
ttc_0.clk_div.change_ph_3      System        SLE                Q                    change_ph_3                                         0.108       7.709
INBUF_DIFF_0                   System        INBUF_DIFF         Y                    INBUF_DIFF_0_Y                                      0.000       7.883
ttc_0.cdr_top.cdr.output_f     System        SLE                Q                    output_f                                            0.108       8.257
ttc_0.clk_div.change_ph_1      System        SLE                Q                    change_ph_1                                         0.108       8.573
ttc_0.clk_div.change_ph_2b     System        SLE                Q                    change_ph_2b                                        0.108       8.728
ttc_0.cdr_top.cdr.data_out     System        SLE                Q                    rx_data_out                                         0.087       8.868
FCCC_1.CCC_INST                System        CCC                LOCK                 LOCK_c                                              0.000       8.874
OSC_0.I_RCOSC_25_50MHZ         System        RCOSC_25_50MHZ     CLKOUT               OSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC     0.000       8.883
==========================================================================================================================================================


Ending Points with Worst Slack
******************************

                            Starting                                       Required          
Instance                    Reference     Type     Pin     Net             Time         Slack
                            Clock                                                            
---------------------------------------------------------------------------------------------
ttc_0.ch_b_det.count[0]     System        SLE      SLn     N_1519_i        9.662        6.948
ttc_0.ch_b_det.count[1]     System        SLE      SLn     N_1519_i        9.662        6.948
ttc_0.ch_b_det.count[2]     System        SLE      SLn     N_1519_i        9.662        6.948
ttc_0.ch_b_det.count[3]     System        SLE      SLn     N_1519_i        9.662        6.948
ttc_0.ch_b_det.count[4]     System        SLE      SLn     N_1519_i        9.662        6.948
ttc_0.ch_b_det.count[0]     System        SLE      EN      count_or[4]     9.662        6.961
ttc_0.ch_b_det.count[1]     System        SLE      EN      count_or[4]     9.662        6.961
ttc_0.ch_b_det.count[2]     System        SLE      EN      count_or[4]     9.662        6.961
ttc_0.ch_b_det.count[3]     System        SLE      EN      count_or[4]     9.662        6.961
ttc_0.ch_b_det.count[4]     System        SLE      EN      count_or[4]     9.662        6.961
=============================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.338
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.662

    - Propagation time:                      2.715
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 6.948

    Number of logic level(s):                2
    Starting point:                          SYSRESET_0 / POWER_ON_RESET_N
    Ending point:                            ttc_0.ch_b_det.count[0] / SLn
    The start point is clocked by            System [rising]
    The end   point is clocked by            clk_div|change_ph_3_inferred_clock [rising] on pin CLK

Instance / Net                               Pin                  Pin               Arrival     No. of    
Name                            Type         Name                 Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------
SYSRESET_0                      SYSRESET     POWER_ON_RESET_N     Out     0.000     0.000       -         
SYSRESET_0_POWER_ON_RESET_N     Net          -                    -       1.126     -           11(3)     
ttc_0.ch_b_det.count_122        CFG2         B                    In      -         1.126       -         
ttc_0.ch_b_det.count_122        CFG2         Y                    Out     0.165     1.291       -         
count_122                       Net          -                    -       0.630     -           2         
ttc_0.ch_b_det.N_1519_i_0       CFG1         A                    In      -         1.921       -         
ttc_0.ch_b_det.N_1519_i_0       CFG1         Y                    Out     0.100     2.021       -         
N_1519_i                        Net          -                    -       0.693     -           5         
ttc_0.ch_b_det.count[0]         SLE          SLn                  In      -         2.715       -         
==========================================================================================================
Total path delay (propagation time + setup) of 3.052 is 0.602(19.7%) logic and 2.450(80.3%) route.
Fanout format: logic fanout (physical fanout)
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report for Trigger_receiver_v1_7 

Mapping to part: m2s050t_esfbga896std
Cell usage:
BUFD            35 uses
CCC             2 uses
CLKINT          5 uses
INV             4 uses
MSS_050         1 use
OR2             1 use
RAM64x18        4 uses
RCOSC_25_50MHZ  1 use
CFG1           16 uses
CFG2           284 uses
CFG3           514 uses
CFG4           829 uses

Carry primitives used for arithmetic functions:
ARI1           323 uses


Sequential Cells: 
SLE            851 uses
Registers not packed on I/O Pads:      851 

DSP Blocks:    0

I/O ports: 51
I/O primitives: 50
INBUF          2 uses
INBUF_DIFF     1 use
OUTBUF         45 uses
SYSRESET       1 use
TRIBUFF        1 use


Global Clock Buffers: 5


RAM/ROM usage summary
Block Rams (RAM64x18) : 4
Total LUTs:    1643

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 54MB peak: 227MB)

Process took 0h:00m:11s realtime, 0h:00m:10s cputime
# Fri Oct 18 11:54:05 2013

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