Synopsys Generic Technology Pre-mapping, Version mapact, Build 976R, Built May 23 2013 12:46:43
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version H-2013.03M-1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

Linked File: Trigger_receiver_v1_7_scck.rpt
Printing clock  summary report in "C:\Microsemi\Projects\Trigger_receiver_v1_7\synthesis\Trigger_receiver_v1_7_scck.rpt" file 
@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 110MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 110MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 111MB)

@N:BN362 : apb_to_dcs.vhd(183) | Removing sequential instance global_reset of view:PrimLib.dffs(prim) in hierarchy view:work.apb_to_dcs(arc) because there are no references to its outputs 
@N:BN362 : apb_to_dcs.vhd(183) | Removing sequential instance rcu_reset of view:PrimLib.dffs(prim) in hierarchy view:work.apb_to_dcs(arc) because there are no references to its outputs 
@N:BN362 : apb_to_dcs.vhd(183) | Removing sequential instance fec_reset of view:PrimLib.dffs(prim) in hierarchy view:work.apb_to_dcs(arc) because there are no references to its outputs 
@N:BN362 : fifocore_sync_scntr.vhd(279) | Removing sequential instance CFIFOliOL of view:PrimLib.dffre(prim) in hierarchy view:corefifo_obf_lib.CFIFOlIL(cfifol) because there are no references to its outputs 
@N:BN362 : fifocore_sync_scntr.vhd(253) | Removing sequential instance CFIFOO0ol of view:PrimLib.dffse(prim) in hierarchy view:corefifo_obf_lib.CFIFOlIL(cfifol) because there are no references to its outputs 
@N:BN362 : mux_arbit.vhd(50) | Removing sequential instance siu_dout[31:0] of view:PrimLib.latr(prim) in hierarchy view:work.MUX_ARBIT(a_muxarbit) because there are no references to its outputs 
@N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance FEE_reset of view:PrimLib.dffr(prim) in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs 
@N:BN362 : sequence_validator.vhd(261) | Removing sequential instance start_of_run of view:PrimLib.dffr(prim) in hierarchy view:work.sequence_validator(behave) because there are no references to its outputs 
@N:BN362 : sequence_validator.vhd(261) | Removing sequential instance end_of_run of view:PrimLib.dffr(prim) in hierarchy view:work.sequence_validator(behave) because there are no references to its outputs 
@N:BN362 : sequence_validator.vhd(261) | Removing sequential instance sync of view:PrimLib.dffr(prim) in hierarchy view:work.sequence_validator(behave) because there are no references to its outputs 
@N:BN362 : broadcast_msg_decoder.vhd(59) | Removing sequential instance eventCnt_reset of view:PrimLib.dffr(prim) in hierarchy view:work.broadcast_message_decoder(behave) because there are no references to its outputs 
@N:BN362 : broadcast_msg_decoder.vhd(57) | Removing sequential instance eventCnt_reset_iRR of view:PrimLib.dffr(prim) in hierarchy view:work.broadcast_message_decoder(behave) because there are no references to its outputs 
@N:BN362 : broadcast_msg_decoder.vhd(70) | Removing sequential instance eventCnt_reset_iR of view:PrimLib.dffr(prim) in hierarchy view:work.broadcast_message_decoder(behave) because there are no references to its outputs 
@W:MT462 : hp_cdr.vhd(64) | Net ttc_0.cdr_top.cdr.clk_out appears to be an unidentified clock source. Assuming default frequency. 
@W:MT462 : hp_cdr.vhd(63) | Net ttc_0.cdr_top.cdr.input_d appears to be an unidentified clock source. Assuming default frequency. 
@W:MT462 : mux_arbit.vhd(52) | Net RCU_DEC_0.U1_MUXARBIT.rcu_data4 appears to be an unidentified clock source. Assuming default frequency. 
@W:MT462 : mux_arbit.vhd(58) | Net RCU_DEC_0.U1_MUXARBIT.un1_rcu_data4 appears to be an unidentified clock source. Assuming default frequency. 
syn_allowed_resources : blockrams=69  set on top level netlist Trigger_receiver_v1_7


Clock Summary
**************

Start                                                        Requested     Requested     Clock        Clock              
Clock                                                        Frequency     Period        Type         Group              
-------------------------------------------------------------------------------------------------------------------------
System                                                       1.0 MHz       1000.000      system       system_clkgroup    
clk_div|change_ph_3_inferred_clock                           100.0 MHz     10.000        inferred     Inferred_clkgroup_0
Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_1
=========================================================================================================================

@W:MT532 : mux_arbit.vhd(50) | Found signal identified as System clock which controls 88 sequential elements including RCU_DEC_0.U1_MUXARBIT.rcu_data[31:0].  Using this clock, which has no specified timing constraint, can adversely impact design performance. 
@W:MT530 : demultiplexab.vhd(57) | Found inferred clock clk_div|change_ph_3_inferred_clock which controls 9 sequential elements including ttc_0.demultiplexAB.ch_b. This clock has no specified timing constraint which may adversely impact design performance. 
@W:MT530 : apb_to_dcs.vhd(141) | Found inferred clock Trigger_receiver_v1_7_FCCC_1_FCCC|GL0_net_inferred_clock which controls 1007 sequential elements including apb_to_dcs_0.timeout_cnt_en. This clock has no specified timing constraint which may adversely impact design performance. 

Finished Pre Mapping Phase.@N: BN225 |Writing default property annotation file C:\Microsemi\Projects\Trigger_receiver_v1_7\synthesis\Trigger_receiver_v1_7.sap.
Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 141MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Oct 18 11:53:53 2013

###########################################################]