#Build: Synplify Pro H-2013.03M-SP1-1 , Build 057R, Sep 24 2013 #install: C:\Microsemi\Libero_v11.2\Synopsys\synplify_H201303MSP1-1 #OS: Windows 7 6.2 #Hostname: WINDOWTOSH #Implementation: synthesis $ Start of Compile #Wed Nov 27 17:13:57 2013 Synopsys VHDL Compiler, version comp201303rcp1, Build 323R, built Sep 30 2013 @N: : | Running in 64-bit mode Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. @N:CD720 : std.vhd(146) | Setting time resolution to ns @N: : Trigger_receiver_v1_7.vhd(20) | Top entity is set to Trigger_receiver_v1_7. Options changed - recompiling VHDL syntax check successful! @N:CD231 : std1164.vhd(913) | Using onehot encoding for type mvl9plus ('U'="1000000000") @N:CD630 : Trigger_receiver_v1_7.vhd(20) | Synthesizing work.trigger_receiver_v1_7.rtl @N:CD630 : smartfusion2.vhd(434) | Synthesizing smartfusion2.bibuf.syn_black_box Post processing for smartfusion2.bibuf.syn_black_box @N:CD630 : smartfusion2.vhd(492) | Synthesizing smartfusion2.inbuf_diff.syn_black_box Post processing for smartfusion2.inbuf_diff.syn_black_box @N:CD630 : ttc.vhd(5) | Synthesizing work.ttc.connect @N:CD630 : ch_b_det.vhd(41) | Synthesizing work.ch_b_det.behavioral Post processing for work.ch_b_det.behavioral @A:CL282 : ch_b_det.vhd(59) | Feedback mux created for signal count[4:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @N:CD630 : demultiplexAB.vhd(39) | Synthesizing work.demultiplexab.behavioral Post processing for work.demultiplexab.behavioral @N:CD630 : clk_div.vhd(39) | Synthesizing work.clk_div.behavioral Post processing for work.clk_div.behavioral @N:CD630 : cdr_top.vhd(43) | Synthesizing work.cdr_top.behave @N:CD630 : hp_cdr.vhd(7) | Synthesizing work.hp_cdr.hp_fig2 Post processing for work.hp_cdr.hp_fig2 @W:CL111 : hp_cdr.vhd(29) | All reachable assignments to err_det assign '0'; register removed by optimization @N:CD630 : smartfusion2.vhd(349) | Synthesizing smartfusion2.bufd.syn_black_box Post processing for smartfusion2.bufd.syn_black_box Post processing for work.cdr_top.behave Post processing for work.ttc.connect @N:CD630 : Trigger_receiver_v1_7_MSS.vhd(17) | Synthesizing work.trigger_receiver_v1_7_mss.rtl @N:CD630 : smartfusion2.vhd(413) | Synthesizing smartfusion2.outbuf.syn_black_box Post processing for smartfusion2.outbuf.syn_black_box @N:CD630 : smartfusion2.vhd(503) | Synthesizing smartfusion2.outbuf_diff.syn_black_box Post processing for smartfusion2.outbuf_diff.syn_black_box @N:CD630 : smartfusion2.vhd(403) | Synthesizing smartfusion2.inbuf.syn_black_box Post processing for smartfusion2.inbuf.syn_black_box @N:CD630 : smartfusion2.vhd(423) | Synthesizing smartfusion2.tribuff.syn_black_box Post processing for smartfusion2.tribuff.syn_black_box @W:CD280 : Trigger_receiver_v1_7_MSS.vhd(171) | Unbound component MSS_050 mapped to black box @N:CD630 : Trigger_receiver_v1_7_MSS.vhd(171) | Synthesizing work.mss_050.syn_black_box Post processing for work.mss_050.syn_black_box Post processing for work.trigger_receiver_v1_7_mss.rtl @N:CD630 : trigger_receiver.vhd(43) | Synthesizing work.trigger_receiver.arc @W:CD326 : trigger_receiver.vhd(306) | Port l2_extendedlatency of entity work.rcu_com_release is unconnected @N:CD630 : counters.vhd(44) | Synthesizing work.counters.arc Post processing for work.counters.arc @N:CD630 : fifo_wrapper.vhd(41) | Synthesizing work.fifo_wrapper.behave @N:CD364 : fifo_wrapper.vhd(163) | Removed redundant assignment @N:CD630 : ms_event_fifo.vhd(19) | Synthesizing work.ms_event_fifo.rtl @N:CD630 : COREFIFO.vhd(13) | Synthesizing corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_corefifo.cfifol @W:CD638 : COREFIFO.vhd(245) | Signal cfifoo1l is undriven @W:CD638 : COREFIFO.vhd(247) | Signal cfifol1l is undriven @W:CD638 : COREFIFO.vhd(253) | Signal cfifol0l is undriven @W:CD638 : COREFIFO.vhd(259) | Signal cfifoi0l is undriven @W:CD638 : COREFIFO.vhd(285) | Signal cfifoi0i is undriven @N:CD630 : ms_event_fifo_ms_event_fifo_0_ram_wrapper.vhd(10) | Synthesizing corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_ram_wrapper.generated @N:CD630 : ms_event_fifo_ms_event_fifo_0_USRAM_top.vhd(8) | Synthesizing corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_usram_top.def_arch @N:CD630 : smartfusion2.vhd(620) | Synthesizing smartfusion2.ram64x18.syn_black_box Post processing for smartfusion2.ram64x18.syn_black_box @N:CD630 : smartfusion2.vhd(575) | Synthesizing smartfusion2.vcc.syn_black_box Post processing for smartfusion2.vcc.syn_black_box @N:CD630 : smartfusion2.vhd(569) | Synthesizing smartfusion2.gnd.syn_black_box Post processing for smartfusion2.gnd.syn_black_box @N:CD630 : smartfusion2.vhd(342) | Synthesizing smartfusion2.inv.syn_black_box Post processing for smartfusion2.inv.syn_black_box Post processing for corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_usram_top.def_arch Post processing for corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_ram_wrapper.generated @N:CD630 : fifocore_sync_scntr.vhd(13) | Synthesizing corefifo_obf_lib.cfifolil.cfifol @W:CD638 : fifocore_sync_scntr.vhd(108) | Signal cfifooiil is undriven Post processing for corefifo_obf_lib.cfifolil.cfifol @W:CL169 : fifocore_sync_scntr.vhd(245) | Pruning register CFIFOL0il @W:CL169 : fifocore_sync_scntr.vhd(237) | Pruning register CFIFOl1OL @W:CL111 : fifocore_sync_scntr.vhd(279) | All reachable assignments to CFIFOoOLl assign '0'; register removed by optimization @W:CL111 : fifocore_sync_scntr.vhd(279) | All reachable assignments to CFIFOLOll assign '0'; register removed by optimization @W:CL111 : fifocore_sync_scntr.vhd(253) | All reachable assignments to CFIFOi1OL assign '0'; register removed by optimization @W:CL111 : fifocore_sync_scntr.vhd(253) | All reachable assignments to CFIFOO1oL assign '0'; register removed by optimization Post processing for corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_corefifo.cfifol Post processing for work.ms_event_fifo.rtl Post processing for work.fifo_wrapper.behave @N:CD630 : phase_check.vhd(37) | Synthesizing work.phase_check.behave Post processing for work.phase_check.behave @N:CD630 : sequence_validator.vhd(40) | Synthesizing work.sequence_validator.behave @N:CD231 : sequence_validator.vhd(93) | Using onehot encoding for type state (s_idle="100000000") @W:CD604 : sequence_validator.vhd(253) | OTHERS clause is not synthesized @W:CD434 : sequence_validator.vhd(189) | Signal timeout_counter in the sensitivity list is not used in the process Post processing for work.sequence_validator.behave @W:CL169 : sequence_validator.vhd(261) | Pruning register timeout_counter(3 downto 0) @W:CL169 : sequence_validator.vhd(261) | Pruning register pre_pulseR @W:CL190 : sequence_validator.vhd(261) | Optimizing register bit prepulse_error to a constant 0 @W:CL169 : sequence_validator.vhd(261) | Pruning register prepulse_error @N:CD630 : L1_line_decoder.vhd(37) | Synthesizing work.l1_line_decoder.behave Post processing for work.l1_line_decoder.behave @N:CD630 : addressed_msg_decoder.vhd(41) | Synthesizing work.addressed_message_decoder.arc @N:CD231 : addressed_msg_decoder.vhd(68) | Using onehot encoding for type state (s_idle="10000000000000") Post processing for work.addressed_message_decoder.arc @N:CD630 : broadcast_msg_decoder.vhd(41) | Synthesizing work.broadcast_message_decoder.behave Post processing for work.broadcast_message_decoder.behave @N:CD630 : hamming_decoder.vhd(39) | Synthesizing work.hamming_decoder.behave Post processing for work.hamming_decoder.behave @N:CD630 : serialb_com.vhd(39) | Synthesizing work.serialb_com.behave @N:CD231 : serialb_com.vhd(55) | Using onehot encoding for type state (s_idle="1000000") @W:CD604 : serialb_com.vhd(148) | OTHERS clause is not synthesized Post processing for work.serialb_com.behave @N:CD630 : rcu_com_release.vhd(41) | Synthesizing work.rcu_com_release.arc Post processing for work.rcu_com_release.arc Post processing for work.trigger_receiver.arc @N:CD630 : smartfusion2.vhd(779) | Synthesizing smartfusion2.sysreset.syn_black_box Post processing for smartfusion2.sysreset.syn_black_box @N:CD630 : rcu_dec.vhd(64) | Synthesizing work.rcu_dec.a_rcudec @W:CD638 : rcu_dec.vhd(449) | Signal d_siu_rst is undriven @N:CD630 : abs_cnt.vhd(27) | Synthesizing work.abs_cnt.a_abscnt @N:CD630 : cnt12.vhd(19) | Synthesizing work.cnt12.a_cnt12 Post processing for work.cnt12.a_cnt12 @N:CD630 : posdge_pulse.vhd(20) | Synthesizing work.posedge_pulse.a_posedge_pulse Post processing for work.posedge_pulse.a_posedge_pulse @N:CD630 : cnt20.vhd(19) | Synthesizing work.cnt20.a_cnt20 Post processing for work.cnt20.a_cnt20 Post processing for work.abs_cnt.a_abscnt @N:CD630 : rcu_reg.vhd(62) | Synthesizing work.rcu_reg.a_rcureg @W:CD434 : rcu_reg.vhd(203) | Signal clk in the sensitivity list is not used in the process @W:CD434 : rcu_reg.vhd(265) | Signal rst in the sensitivity list is not used in the process Post processing for work.rcu_reg.a_rcureg @W:CL117 : rcu_reg.vhd(205) | Latch generated from process for signal st_meb_full; possible missing assignment in an if or case statement. @N:CD630 : cmd_decoder.vhd(21) | Synthesizing work.cmd_decoder.a_cmddecoder Post processing for work.cmd_decoder.a_cmddecoder @N:CD630 : addr_decoder.vhd(23) | Synthesizing work.addr_decoder.a_addrdecoder Post processing for work.addr_decoder.a_addrdecoder @N:CD630 : arbit.vhd(15) | Synthesizing work.arbit.a_arbit @N:CD233 : arbit.vhd(36) | Using sequential encoding for type sm @W:CD604 : arbit.vhd(110) | OTHERS clause is not synthesized @W:CD604 : arbit.vhd(139) | OTHERS clause is not synthesized Post processing for work.arbit.a_arbit @N:CD630 : mux_arbit.vhd(20) | Synthesizing work.mux_arbit.a_muxarbit Post processing for work.mux_arbit.a_muxarbit @W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal siu_dout(31 downto 0); possible missing assignment in an if or case statement. @W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal rcu_data(31 downto 0); possible missing assignment in an if or case statement. @W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal dcs_dout(31 downto 0); possible missing assignment in an if or case statement. @W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal rcu_add(15 downto 0); possible missing assignment in an if or case statement. @W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal rcu_we; possible missing assignment in an if or case statement. Post processing for work.rcu_dec.a_rcudec @N:CD630 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(8) | Synthesizing work.trigger_receiver_v1_7_osc_0_osc.def_arch @N:CD630 : osc_comps.vhd(39) | Synthesizing work.xtlosc.def_arch Post processing for work.xtlosc.def_arch Post processing for work.trigger_receiver_v1_7_osc_0_osc.def_arch @W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(16) | XTLOSC_O2F is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(14) | RCOSC_1MHZ_O2F is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(13) | RCOSC_1MHZ_CCC is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(12) | RCOSC_25_50MHZ_O2F is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(11) | RCOSC_25_50MHZ_CCC is not assigned a value (floating) -- simulation mismatch possible. @N:CD630 : smartfusion2.vhd(207) | Synthesizing smartfusion2.or2.syn_black_box Post processing for smartfusion2.or2.syn_black_box @N:CD630 : Trigger_receiver_v1_7_FCCC_2_FCCC.vhd(8) | Synthesizing work.trigger_receiver_v1_7_fccc_2_fccc.def_arch @N:CD630 : smartfusion2.vhd(787) | Synthesizing smartfusion2.ccc.syn_black_box Post processing for smartfusion2.ccc.syn_black_box @N:CD630 : smartfusion2.vhd(562) | Synthesizing smartfusion2.clkint.syn_black_box Post processing for smartfusion2.clkint.syn_black_box Post processing for work.trigger_receiver_v1_7_fccc_2_fccc.def_arch @N:CD630 : Trigger_receiver_v1_7_FCCC_1_FCCC.vhd(8) | Synthesizing work.trigger_receiver_v1_7_fccc_1_fccc.def_arch Post processing for work.trigger_receiver_v1_7_fccc_1_fccc.def_arch @N:CD630 : Trigger_receiver_v1_7_FCCC_0_FCCC.vhd(8) | Synthesizing work.trigger_receiver_v1_7_fccc_0_fccc.def_arch Post processing for work.trigger_receiver_v1_7_fccc_0_fccc.def_arch @N:CD630 : coresf2reset.vhd(85) | Synthesizing work.coresf2reset.rtl @W:CD434 : coresf2reset.vhd(285) | Signal fpll_lock in the sensitivity list is not used in the process @W:CD434 : coresf2reset.vhd(293) | Signal sdif0_spll_lock in the sensitivity list is not used in the process @W:CD434 : coresf2reset.vhd(301) | Signal sdif1_spll_lock in the sensitivity list is not used in the process @W:CD434 : coresf2reset.vhd(309) | Signal sdif2_spll_lock in the sensitivity list is not used in the process @W:CD434 : coresf2reset.vhd(317) | Signal sdif3_spll_lock in the sensitivity list is not used in the process Post processing for work.coresf2reset.rtl @N:CL177 : coresf2reset.vhd(672) | Sharing sequential element M3_RESET_N_0. @N:CL177 : coresf2reset.vhd(448) | Sharing sequential element sdif2_spll_lock_q1. @N:CL177 : coresf2reset.vhd(448) | Sharing sequential element sdif1_spll_lock_q1. @N:CL177 : coresf2reset.vhd(448) | Sharing sequential element sdif0_spll_lock_q1. @N:CL177 : coresf2reset.vhd(448) | Sharing sequential element fpll_lock_q1. @N:CD630 : coresf2config.vhd(25) | Synthesizing work.coresf2config.rtl Post processing for work.coresf2config.rtl @N:CD630 : coreapb3.vhd(14) | Synthesizing coreapb3_lib.coreapb3.capb3ioi @W:CD604 : coreapb3.vhd(440) | OTHERS clause is not synthesized @W:CD638 : coreapb3.vhd(364) | Signal capb3olil is undriven @N:CD630 : coreapb3_muxptob3.vhd(14) | Synthesizing coreapb3_lib.capb3il.capb3o0 Post processing for coreapb3_lib.capb3il.capb3o0 Post processing for coreapb3_lib.coreapb3.capb3ioi @N:CD630 : apb_to_dcs.vhd(9) | Synthesizing work.apb_to_dcs.arc @N:CD233 : apb_to_dcs.vhd(53) | Using sequential encoding for type state @W:CD604 : apb_to_dcs.vhd(131) | OTHERS clause is not synthesized Post processing for work.apb_to_dcs.arc Post processing for work.trigger_receiver_v1_7.rtl @N:CL201 : apb_to_dcs.vhd(96) | Trying to extract state machine for register current_state Extracted state machine for register current_state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL246 : apb_to_dcs.vhd(21) | Input port bits 31 to 20 of paddr(31 downto 0) are unused @W:CL159 : coreapb3.vhd(50) | Input iaddR is unused @W:CL159 : coreapb3.vhd(51) | Input PRESetn is unused @W:CL159 : coreapb3.vhd(52) | Input PCLK is unused @W:CL159 : coreapb3.vhd(82) | Input prdataS0 is unused @W:CL159 : coreapb3.vhd(83) | Input PRdatas1 is unused @W:CL159 : coreapb3.vhd(84) | Input Prdatas2 is unused @W:CL159 : coreapb3.vhd(85) | Input prdatAS3 is unused @W:CL159 : coreapb3.vhd(86) | Input PRDATAS4 is unused @W:CL159 : coreapb3.vhd(88) | Input prdataS6 is unused @W:CL159 : coreapb3.vhd(89) | Input PRDATAs7 is unused @W:CL159 : coreapb3.vhd(90) | Input prdatas8 is unused @W:CL159 : coreapb3.vhd(91) | Input PRDATas9 is unused @W:CL159 : coreapb3.vhd(92) | Input PRDATAs10 is unused @W:CL159 : coreapb3.vhd(93) | Input PRdatas11 is unused @W:CL159 : coreapb3.vhd(94) | Input PRDATas12 is unused @W:CL159 : coreapb3.vhd(95) | Input PRDatas13 is unused @W:CL159 : coreapb3.vhd(96) | Input PRDATAS14 is unused @W:CL159 : coreapb3.vhd(97) | Input PRDATAS15 is unused @W:CL159 : coreapb3.vhd(99) | Input PREadys0 is unused @W:CL159 : coreapb3.vhd(100) | Input preadys1 is unused @W:CL159 : coreapb3.vhd(101) | Input preadys2 is unused @W:CL159 : coreapb3.vhd(102) | Input preadys3 is unused @W:CL159 : coreapb3.vhd(103) | Input PREADYS4 is unused @W:CL159 : coreapb3.vhd(105) | Input preadys6 is unused @W:CL159 : coreapb3.vhd(106) | Input preadys7 is unused @W:CL159 : coreapb3.vhd(107) | Input Preadys8 is unused @W:CL159 : coreapb3.vhd(108) | Input PReadys9 is unused @W:CL159 : coreapb3.vhd(109) | Input preadys10 is unused @W:CL159 : coreapb3.vhd(110) | Input PREADYS11 is unused @W:CL159 : coreapb3.vhd(111) | Input pREADYS12 is unused @W:CL159 : coreapb3.vhd(112) | Input preadyS13 is unused @W:CL159 : coreapb3.vhd(113) | Input PREAdys14 is unused @W:CL159 : coreapb3.vhd(114) | Input Preadys15 is unused @W:CL159 : coreapb3.vhd(116) | Input PSLVerrs0 is unused @W:CL159 : coreapb3.vhd(117) | Input pslverrs1 is unused @W:CL159 : coreapb3.vhd(118) | Input PSlverrs2 is unused @W:CL159 : coreapb3.vhd(119) | Input PSLVERRS3 is unused @W:CL159 : coreapb3.vhd(120) | Input pslverRS4 is unused @W:CL159 : coreapb3.vhd(122) | Input PSLVERRS6 is unused @W:CL159 : coreapb3.vhd(123) | Input Pslverrs7 is unused @W:CL159 : coreapb3.vhd(124) | Input PSLVErrs8 is unused @W:CL159 : coreapb3.vhd(125) | Input pslVERRS9 is unused @W:CL159 : coreapb3.vhd(126) | Input PSLVERrs10 is unused @W:CL159 : coreapb3.vhd(127) | Input PSLverrs11 is unused @W:CL159 : coreapb3.vhd(128) | Input PSLVERRS12 is unused @W:CL159 : coreapb3.vhd(129) | Input pslverrs13 is unused @W:CL159 : coreapb3.vhd(130) | Input Pslverrs14 is unused @W:CL159 : coreapb3.vhd(131) | Input pslverRS15 is unused @N:CL201 : coresf2config.vhd(396) | Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL177 : coresf2reset.vhd(448) | Sharing sequential element fpll_lock_q2. @N:CL177 : coresf2reset.vhd(448) | Sharing sequential element sdif0_spll_lock_q2. @N:CL177 : coresf2reset.vhd(448) | Sharing sequential element sdif1_spll_lock_q2. @N:CL177 : coresf2reset.vhd(448) | Sharing sequential element sdif2_spll_lock_q2. @N:CL201 : coresf2reset.vhd(717) | Trying to extract state machine for register sm2_state Extracted state machine for register sm2_state State machine has 2 reachable states with original encodings of: 000 001 @N:CL201 : coresf2reset.vhd(579) | Trying to extract state machine for register sm0_state Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W:CL159 : coresf2reset.vhd(145) | Input FPLL_LOCK is unused @W:CL159 : coresf2reset.vhd(148) | Input SDIF0_SPLL_LOCK is unused @W:CL159 : coresf2reset.vhd(152) | Input SDIF1_SPLL_LOCK is unused @W:CL159 : coresf2reset.vhd(156) | Input SDIF2_SPLL_LOCK is unused @W:CL159 : coresf2reset.vhd(160) | Input SDIF3_SPLL_LOCK is unused @N:CL201 : arbit.vhd(44) | Trying to extract state machine for register pr_st Extracted state machine for register pr_st State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL159 : rcu_dec.vhd(197) | Input fsmrd_st_a is unused @W:CL159 : rcu_dec.vhd(198) | Input fsmwr_st_b is unused @N:CL201 : serialb_com.vhd(72) | Trying to extract state machine for register current_state Extracted state machine for register current_state State machine has 7 reachable states with original encodings of: 0000001 0000010 0000100 0001000 0010000 0100000 1000000 @W:CL246 : broadcast_msg_decoder.vhd(45) | Input port bits 7 to 3 of brcdata(7 downto 0) are unused @N:CL201 : sequence_validator.vhd(172) | Trying to extract state machine for register current_state Extracted state machine for register current_state State machine has 9 reachable states with original encodings of: 000000001 000000010 000000100 000001000 000010000 000100000 001000000 010000000 100000000 @W:CL159 : sequence_validator.vhd(46) | Input pre_pulse is unused @W:CL159 : sequence_validator.vhd(71) | Input L1_msg_tw_passed is unused @W:CL159 : ms_event_fifo_ms_event_fifo_0_ram_wrapper.vhd(27) | Input RCLOCK is unused @W:CL159 : ms_event_fifo_ms_event_fifo_0_ram_wrapper.vhd(28) | Input WCLOCK is unused @W:CL159 : COREFIFO.vhd(62) | Input MEmrD is unused @END At c_vhdl Exit (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 114MB peak: 140MB) Process took 0h:00m:17s realtime, 0h:00m:17s cputime # Wed Nov 27 17:14:14 2013 ###########################################################] Premap Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1085R, Built Oct 16 2013 12:01:22 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version H-2013.03M-SP1-1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) Reading constraint file: C:\Actelprj\System_w_Linux_11_2\constraint\Trigger_receiver_1_7_synplify.sdc Linked File: Trigger_receiver_v1_7_scck.rpt Printing clock summary report in "C:\Actelprj\System_w_Linux_11_2\synthesis\Trigger_receiver_v1_7_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 111MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 111MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 111MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 112MB) @W:BN132 : coresf2reset.vhd(579) | Removing sequential instance CoreSF2Reset_0.MDDR_DDR_AXI_S_CORE_RESET_N_0, because it is equivalent to instance CoreSF2Reset_0.FDDR_CORE_RESET_N_0 @W:BN132 : coresf2reset.vhd(579) | Removing sequential instance CoreSF2Reset_0.SDIF3_PHY_RESET_N_0, because it is equivalent to instance CoreSF2Reset_0.SDIF2_PHY_RESET_N_0 @W:BN132 : coresf2reset.vhd(579) | Removing sequential instance CoreSF2Reset_0.SDIF2_PHY_RESET_N_0, because it is equivalent to instance CoreSF2Reset_0.SDIF1_PHY_RESET_N_0 @W:BN132 : coresf2reset.vhd(579) | Removing sequential instance CoreSF2Reset_0.SDIF1_PHY_RESET_N_0, because it is equivalent to instance CoreSF2Reset_0.SDIF0_PHY_RESET_N_0 @W:BN132 : coresf2reset.vhd(579) | Removing sequential instance CoreSF2Reset_0.SDIF3_CORE_RESET_N_0, because it is equivalent to instance CoreSF2Reset_0.SDIF2_CORE_RESET_N_0 @W:BN132 : coresf2reset.vhd(579) | Removing sequential instance CoreSF2Reset_0.SDIF2_CORE_RESET_N_0, because it is equivalent to instance CoreSF2Reset_0.SDIF1_CORE_RESET_N_0 @W:BN132 : coresf2reset.vhd(579) | Removing sequential instance CoreSF2Reset_0.SDIF1_CORE_RESET_N_0, because it is equivalent to instance CoreSF2Reset_0.SDIF0_CORE_RESET_N_0 @N:BN362 : apb_to_dcs.vhd(181) | Removing sequential instance global_reset of view:PrimLib.dffs(prim) in hierarchy view:work.apb_to_dcs(arc) because there are no references to its outputs @N:BN362 : apb_to_dcs.vhd(181) | Removing sequential instance rcu_reset of view:PrimLib.dffs(prim) in hierarchy view:work.apb_to_dcs(arc) because there are no references to its outputs @N:BN362 : apb_to_dcs.vhd(181) | Removing sequential instance fec_reset of view:PrimLib.dffs(prim) in hierarchy view:work.apb_to_dcs(arc) because there are no references to its outputs @N:BN362 : coresf2config.vhd(407) | Removing sequential instance FDDR_PENABLE_0 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(407) | Removing sequential instance SDIF0_PENABLE_0 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(407) | Removing sequential instance SDIF1_PENABLE_0 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(407) | Removing sequential instance SDIF2_PENABLE_0 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(407) | Removing sequential instance SDIF3_PENABLE_0 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2reset.vhd(717) | Removing sequential instance EXT_RESET_OUT_0 of view:PrimLib.dffse(prim) in hierarchy view:work.CoreSF2Reset(rtl) because there are no references to its outputs @N:BN362 : coresf2reset.vhd(672) | Removing sequential instance MSS_RESET_N_F2M_0 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Reset(rtl) because there are no references to its outputs @N:BN362 : coresf2reset.vhd(579) | Removing sequential instance USER_FAB_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreSF2Reset(rtl) because there are no references to its outputs @N:BN362 : coresf2reset.vhd(579) | Removing sequential instance FDDR_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreSF2Reset(rtl) because there are no references to its outputs @N:BN362 : coresf2reset.vhd(579) | Removing sequential instance SDIF0_PHY_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreSF2Reset(rtl) because there are no references to its outputs @N:BN362 : coresf2reset.vhd(579) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreSF2Reset(rtl) because there are no references to its outputs @N:BN362 : fifocore_sync_scntr.vhd(279) | Removing sequential instance CFIFOliOL of view:PrimLib.dffre(prim) in hierarchy view:corefifo_obf_lib.CFIFOlIL(cfifol) because there are no references to its outputs @N:BN362 : fifocore_sync_scntr.vhd(253) | Removing sequential instance CFIFOO0ol of view:PrimLib.dffse(prim) in hierarchy view:corefifo_obf_lib.CFIFOlIL(cfifol) because there are no references to its outputs @N:BN362 : mux_arbit.vhd(50) | Removing sequential instance siu_dout[31:0] of view:PrimLib.latr(prim) in hierarchy view:work.MUX_ARBIT(a_muxarbit) because there are no references to its outputs @N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance FEE_reset of view:PrimLib.dffr(prim) in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs @N:BN362 : sequence_validator.vhd(261) | Removing sequential instance start_of_run of view:PrimLib.dffr(prim) in hierarchy view:work.sequence_validator(behave) because there are no references to its outputs @N:BN362 : sequence_validator.vhd(261) | Removing sequential instance end_of_run of view:PrimLib.dffr(prim) in hierarchy view:work.sequence_validator(behave) because there are no references to its outputs @N:BN362 : sequence_validator.vhd(261) | Removing sequential instance sync of view:PrimLib.dffr(prim) in hierarchy view:work.sequence_validator(behave) because there are no references to its outputs @N:BN362 : broadcast_msg_decoder.vhd(59) | Removing sequential instance eventCnt_reset of view:PrimLib.dffr(prim) in hierarchy view:work.broadcast_message_decoder(behave) because there are no references to its outputs @N:BN362 : coresf2reset.vhd(717) | Removing sequential instance sm2_state[0:1] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreSF2Reset(rtl) because there are no references to its outputs @N:BN362 : coresf2reset.vhd(579) | Removing sequential instance release_ext_reset of view:PrimLib.dffre(prim) in hierarchy view:work.CoreSF2Reset(rtl) because there are no references to its outputs @N:BN362 : coresf2reset.vhd(395) | Removing sequential instance sm1_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Reset(rtl) because there are no references to its outputs @N:BN362 : broadcast_msg_decoder.vhd(57) | Removing sequential instance eventCnt_reset_iRR of view:PrimLib.dffr(prim) in hierarchy view:work.broadcast_message_decoder(behave) because there are no references to its outputs @N:BN362 : coresf2reset.vhd(395) | Removing sequential instance sm1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Reset(rtl) because there are no references to its outputs @N:BN362 : broadcast_msg_decoder.vhd(70) | Removing sequential instance eventCnt_reset_iR of view:PrimLib.dffr(prim) in hierarchy view:work.broadcast_message_decoder(behave) because there are no references to its outputs @N:BN115 : corefifo.vhd(527) | Removing instance RW1\.CFIFOoi1 of view:corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_ram_wrapper(generated) because there are no references to its outputs @N:BN362 : coresf2reset.vhd(406) | Removing sequential instance sm2_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Reset(rtl) because there are no references to its outputs @N:BN115 : ms_event_fifo_ms_event_fifo_0_ram_wrapper.vhd(60) | Removing instance U5_syncnonpipe of view:corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_USRAM_top(def_arch) because there are no references to its outputs @N:BN362 : coresf2reset.vhd(406) | Removing sequential instance sm2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Reset(rtl) because there are no references to its outputs @N:BN114 : ms_event_fifo_ms_event_fifo_0_usram_top.vhd(118) | Removing instance ms_event_fifo_ms_event_fifo_0_USRAM_top_R0C0 of black_box view:smartfusion2.RAM64x18(syn_black_box) because there are no references to its outputs @N:BN114 : ms_event_fifo_ms_event_fifo_0_usram_top.vhd(228) | Removing instance ms_event_fifo_ms_event_fifo_0_USRAM_top_R0C1 of black_box view:smartfusion2.RAM64x18(syn_black_box) because there are no references to its outputs @N:BN114 : ms_event_fifo_ms_event_fifo_0_usram_top.vhd(174) | Removing instance ms_event_fifo_ms_event_fifo_0_USRAM_top_R0C2 of black_box view:smartfusion2.RAM64x18(syn_black_box) because there are no references to its outputs @N:BN114 : ms_event_fifo_ms_event_fifo_0_usram_top.vhd(284) | Removing instance ms_event_fifo_ms_event_fifo_0_USRAM_top_R0C3 of black_box view:smartfusion2.RAM64x18(syn_black_box) because there are no references to its outputs @W:MT462 : hp_cdr.vhd(64) | Net ttc_0.cdr_top.cdr.clk_out appears to be an unidentified clock source. Assuming default frequency. @W:MT462 : hp_cdr.vhd(63) | Net ttc_0.cdr_top.cdr.input_d appears to be an unidentified clock source. Assuming default frequency. @W:MT462 : mux_arbit.vhd(52) | Net RCU_DEC_0.U1_MUXARBIT.rcu_data4 appears to be an unidentified clock source. Assuming default frequency. @W:MT462 : mux_arbit.vhd(58) | Net RCU_DEC_0.U1_MUXARBIT.un1_rcu_data4 appears to be an unidentified clock source. Assuming default frequency. syn_allowed_resources : blockrams=69 set on top level netlist Trigger_receiver_v1_7 Clock Summary ************** Start Requested Requested Clock Clock Clock Frequency Period Type Group -------------------------------------------------------------------------------------------------------------------------- System 1.0 MHz 1000.000 system system_clkgroup GL2_net_inferred_clock 40.0 MHz 25.000 declared Inferred_clkgrp_4 MAC_MII_RX_CLK 25.0 MHz 40.000 declared MAC_Clocks MAC_MII_TX_CLK 25.0 MHz 40.000 declared MAC_Clocks clk_div|change_ph_3_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 ========================================================================================================================== @W:MT532 : mux_arbit.vhd(50) | Found signal identified as System clock which controls 88 sequential elements including RCU_DEC_0.U1_MUXARBIT.rcu_data[31:0]. Using this clock, which has no specified timing constraint, can adversely impact design performance. @W:MT530 : demultiplexab.vhd(57) | Found inferred clock clk_div|change_ph_3_inferred_clock which controls 9 sequential elements including ttc_0.demultiplexAB.ch_b. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coresf2reset.vhd(732) | Found inferred clock Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock which controls 33 sequential elements including CoreSF2Reset_0.count[13:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coresf2config.vhd(396) | Found inferred clock Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 92 sequential elements including CoreSF2Config_0.FIC_2_APB_M_PREADY_0. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\Actelprj\System_w_Linux_11_2\synthesis\Trigger_receiver_v1_7.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 77MB peak: 141MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Wed Nov 27 17:14:18 2013 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1085R, Built Oct 16 2013 12:01:22 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version H-2013.03M-SP1-1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 138MB peak: 140MB) @N:BN362 : fifocore_sync_scntr.vhd(315) | Removing sequential instance microsemi_version\.CDH_fifo.ms_event_fifo_0.CFIFOl10\.CFIFOi10.CFIFOI0ol[6:0] of view:PrimLib.dffr(prim) in hierarchy view:work.fifo_wrapper(behave) because there are no references to its outputs @N:BN362 : fifocore_sync_scntr.vhd(305) | Removing sequential instance microsemi_version\.CDH_fifo.ms_event_fifo_0.CFIFOl10\.CFIFOi10.CFIFOl0OL[6:0] of view:PrimLib.dffr(prim) in hierarchy view:work.fifo_wrapper(behave) because there are no references to its outputs @W:MO171 : phase_check.vhd(54) | Sequential instance trigger_receiver_0.phase_check.phase_checker.sclkR reduced to a combinational gate by constant propagation @W:MO171 : posdge_pulse.vhd(37) | Sequential instance RCU_DEC_0.U6_ABSCNT.U3_TRSFPULSEA.dff_out1 reduced to a combinational gate by constant propagation @W:MO171 : posdge_pulse.vhd(37) | Sequential instance RCU_DEC_0.U6_ABSCNT.U4_TRSFPULSEB.dff_out1 reduced to a combinational gate by constant propagation @W:MO171 : posdge_pulse.vhd(37) | Sequential instance RCU_DEC_0.U6_ABSCNT.U5_ACKPULSEA.dff_out1 reduced to a combinational gate by constant propagation @W:MO171 : posdge_pulse.vhd(37) | Sequential instance RCU_DEC_0.U6_ABSCNT.U6_ACKPULSEB.dff_out1 reduced to a combinational gate by constant propagation @W:MO171 : posdge_pulse.vhd(37) | Sequential instance RCU_DEC_0.U6_ABSCNT.U7_CSTBPULSEA.dff_out1 reduced to a combinational gate by constant propagation @W:MO171 : posdge_pulse.vhd(37) | Sequential instance RCU_DEC_0.U6_ABSCNT.U8_CSTBPULSEB.dff_out1 reduced to a combinational gate by constant propagation @N:BN362 : arbit.vhd(44) | Removing sequential instance pr_st[0:2] of view:PrimLib.statemachine(prim) in hierarchy view:work.ARBIT(a_arbit) because there are no references to its outputs @N:BN362 : fifocore_sync_scntr.vhd(253) | Removing sequential instance FIFO.microsemi_version\.CDH_fifo.ms_event_fifo_0.CFIFOl10\.CFIFOi10.CFIFOiIOL of view:PrimLib.dffse(prim) in hierarchy view:work.trigger_receiver(arc) because there are no references to its outputs @N:BN115 : rcu_dec.vhd(562) | Removing instance RCU_DEC_0.U2_ARBIT of view:work.ARBIT(a_arbit) because there are no references to its outputs @W:BN132 : rcu_dec.vhd(729) | Removing sequential instance RCU_DEC_0.blk_err_reg, because it is equivalent to instance RCU_DEC_0.add_err_reg @W:BN132 : rcu_dec.vhd(516) | Removing sequential instance RCU_DEC_0.scel_err_reg[5], because it is equivalent to instance RCU_DEC_0.add_err_reg @W:BN132 : abs_cnt.vhd(109) | Removing user instance RCU_DEC_0.U6_ABSCNT.U2_DSTBCNTB, because it is equivalent to instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA @W:BN132 : abs_cnt.vhd(200) | Removing user instance RCU_DEC_0.U6_ABSCNT.U8_CSTBCNTB, because it is equivalent to instance RCU_DEC_0.U6_ABSCNT.U7_CSTBCNTA @W:BN132 : abs_cnt.vhd(185) | Removing user instance RCU_DEC_0.U6_ABSCNT.U7_CSTBCNTA, because it is equivalent to instance RCU_DEC_0.U6_ABSCNT.U6_ACKCNTB @W:BN132 : abs_cnt.vhd(169) | Removing user instance RCU_DEC_0.U6_ABSCNT.U6_ACKCNTB, because it is equivalent to instance RCU_DEC_0.U6_ABSCNT.U5_ACKCNTA @W:BN132 : abs_cnt.vhd(139) | Removing user instance RCU_DEC_0.U6_ABSCNT.U4_TRSFCNTB, because it is equivalent to instance RCU_DEC_0.U6_ABSCNT.U5_ACKCNTA @W:BN132 : abs_cnt.vhd(124) | Removing user instance RCU_DEC_0.U6_ABSCNT.U3_TRSFCNTA, because it is equivalent to instance RCU_DEC_0.U6_ABSCNT.U5_ACKCNTA Available hyper_sources - for debug and ip models None Found @W:MT462 : hp_cdr.vhd(64) | Net ttc_0.cdr_top.cdr.clk_out appears to be an unidentified clock source. Assuming default frequency. @W:MT462 : hp_cdr.vhd(63) | Net ttc_0.cdr_top.cdr.input_d appears to be an unidentified clock source. Assuming default frequency. @N:BN362 : fifo_wrapper.vhd(129) | Removing sequential instance FIFO.write_counter[3:0] of view:PrimLib.dffr(prim) in hierarchy view:work.trigger_receiver(arc) because there are no references to its outputs @N:BN362 : fifo_wrapper.vhd(129) | Removing sequential instance FIFO.writing of view:PrimLib.dffre(prim) in hierarchy view:work.trigger_receiver(arc) because there are no references to its outputs @N:BN362 : fifocore_sync_scntr.vhd(216) | Removing sequential instance FIFO.microsemi_version\.CDH_fifo.ms_event_fifo_0.CFIFOl10\.CFIFOi10.CFIFOlOOi[7:0] of view:PrimLib.dffr(prim) in hierarchy view:work.trigger_receiver(arc) because there are no references to its outputs @N:BN362 : fifocore_sync_scntr.vhd(279) | Removing sequential instance FIFO.microsemi_version\.CDH_fifo.ms_event_fifo_0.CFIFOl10\.CFIFOi10.CFIFOoiOL of view:PrimLib.dffre(prim) in hierarchy view:work.trigger_receiver(arc) because there are no references to its outputs @W:BN132 : rcu_dec.vhd(743) | Removing sequential instance RCU_DEC_0.chadd_err_cnt_r[11:0], because it is equivalent to instance RCU_DEC_0.bl_err_cnt_r[11:0] Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 138MB peak: 141MB) @W:BN132 : rcu_dec.vhd(527) | Removing instance RCU_DEC_0.scel_err_reg[0], because it is equivalent to instance RCU_DEC_0.add_err_reg @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[0] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[1] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[2] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[3] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[4] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[5] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[6] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[7] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[8] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[9] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[10] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[11] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[12] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[13] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[14] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[15] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[16] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[17] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[18] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[19] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[20] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[21] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[22] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[23] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[24] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[25] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[26] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[27] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[28] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[29] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[30] reduced to a combinational gate by constant propagation @W:MO129 : mux_arbit.vhd(50) | Sequential instance RCU_DEC_0.U1_MUXARBIT.dcs_dout[31] reduced to a combinational gate by constant propagation @N:BN362 : rcu_dec.vhd(527) | Removing sequential instance RCU_DEC_0.scel_err_reg[1] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : rcu_dec.vhd(527) | Removing sequential instance RCU_DEC_0.scel_err_reg[2] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : rcu_dec.vhd(527) | Removing sequential instance RCU_DEC_0.scel_err_reg[3] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : rcu_dec.vhd(527) | Removing sequential instance RCU_DEC_0.scel_err_reg[4] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : rcu_dec.vhd(743) | Removing sequential instance RCU_DEC_0.add_err_reg in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs Encoding state machine current_state[0:3] (view:work.apb_to_dcs(arc)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @W:MO129 : apb_to_dcs.vhd(96) | Sequential instance apb_to_dcs_0.current_state[0] reduced to a combinational gate by constant propagation Encoding state machine state[0:2] (view:work.CoreSF2Config(rtl)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:BN362 : coresf2config.vhd(237) | Removing sequential instance paddr[11] in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(237) | Removing sequential instance pwdata[16] in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(237) | Removing sequential instance pwdata[17] in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(237) | Removing sequential instance pwdata[18] in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(237) | Removing sequential instance pwdata[19] in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(237) | Removing sequential instance pwdata[20] in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(237) | Removing sequential instance pwdata[21] in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(237) | Removing sequential instance pwdata[22] in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(237) | Removing sequential instance pwdata[23] in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(237) | Removing sequential instance pwdata[24] in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(237) | Removing sequential instance pwdata[25] in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(237) | Removing sequential instance pwdata[26] in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(237) | Removing sequential instance pwdata[27] in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(237) | Removing sequential instance pwdata[28] in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(237) | Removing sequential instance pwdata[29] in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(237) | Removing sequential instance pwdata[30] in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(237) | Removing sequential instance pwdata[31] in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @W:BN132 : coresf2config.vhd(501) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[31], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[30] @W:BN132 : coresf2config.vhd(501) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[30], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[29] @W:BN132 : coresf2config.vhd(501) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[29], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[28] @W:BN132 : coresf2config.vhd(501) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[28], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[27] @W:BN132 : coresf2config.vhd(501) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[27], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[26] @W:BN132 : coresf2config.vhd(501) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[26], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[25] @W:BN132 : coresf2config.vhd(501) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[25], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[24] @W:BN132 : coresf2config.vhd(501) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[24], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[23] @W:BN132 : coresf2config.vhd(501) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[23], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[22] @W:BN132 : coresf2config.vhd(501) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[22], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[21] @W:BN132 : coresf2config.vhd(501) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[21], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[20] @W:BN132 : coresf2config.vhd(501) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[20], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[19] @W:BN132 : coresf2config.vhd(501) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[19], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[18] @W:BN132 : coresf2config.vhd(501) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[18], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[17] @W:BN132 : coresf2config.vhd(501) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[17], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[16] @N:BN362 : coresf2config.vhd(501) | Removing sequential instance FIC_2_APB_M_PRDATA_0[16] in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(237) | Removing sequential instance paddr[16] in hierarchy view:work.CoreSF2Config(rtl) because there are no references to its outputs Encoding state machine sm0_state[0:6] (view:work.CoreSF2Reset(rtl)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @N: : coresf2reset.vhd(732) | Found counter in view:work.CoreSF2Reset(rtl) inst count[13:0] @N:BN362 : coresf2reset.vhd(563) | Removing sequential instance sm0_state[0] in hierarchy view:work.CoreSF2Reset(rtl) because there are no references to its outputs @N:BN362 : cmd_decoder.vhd(53) | Removing sequential instance cmd_vector[7] of view:PrimLib.dffr(prim) in hierarchy view:work.CMD_DECODER(a_cmddecoder) because there are no references to its outputs @N:BN362 : cmd_decoder.vhd(53) | Removing sequential instance cmd_vector[0] of view:PrimLib.dffr(prim) in hierarchy view:work.CMD_DECODER(a_cmddecoder) because there are no references to its outputs @N:BN362 : cmd_decoder.vhd(53) | Removing sequential instance cmd_vector[1] of view:PrimLib.dffr(prim) in hierarchy view:work.CMD_DECODER(a_cmddecoder) because there are no references to its outputs @N:BN362 : cmd_decoder.vhd(53) | Removing sequential instance cmd_vector[2] of view:PrimLib.dffr(prim) in hierarchy view:work.CMD_DECODER(a_cmddecoder) because there are no references to its outputs @N:BN362 : cmd_decoder.vhd(53) | Removing sequential instance cmd_vector[3] of view:PrimLib.dffr(prim) in hierarchy view:work.CMD_DECODER(a_cmddecoder) because there are no references to its outputs @N:BN362 : cmd_decoder.vhd(53) | Removing sequential instance cmd_vector[6] of view:PrimLib.dffr(prim) in hierarchy view:work.CMD_DECODER(a_cmddecoder) because there are no references to its outputs @N:BN362 : rcu_reg.vhd(212) | Removing sequential instance rdrx_reg in hierarchy view:work.RCU_REG(a_rcureg) because there are no references to its outputs @N: : cnt20.vhd(38) | Found counter in view:work.CNT20(a_cnt20) inst cnt[19:0] @W:MO160 : cnt12.vhd(37) | Register bit cnt[11] is always 0, optimizing ... @W:MO160 : cnt12.vhd(37) | Register bit cnt[10] is always 0, optimizing ... @W:MO160 : cnt12.vhd(37) | Register bit cnt[9] is always 0, optimizing ... @W:MO160 : cnt12.vhd(37) | Register bit cnt[8] is always 0, optimizing ... @W:MO160 : cnt12.vhd(37) | Register bit cnt[7] is always 0, optimizing ... @W:MO160 : cnt12.vhd(37) | Register bit cnt[6] is always 0, optimizing ... @W:MO160 : cnt12.vhd(37) | Register bit cnt[5] is always 0, optimizing ... @W:MO160 : cnt12.vhd(37) | Register bit cnt[4] is always 0, optimizing ... @W:MO160 : cnt12.vhd(37) | Register bit cnt[3] is always 0, optimizing ... @W:MO160 : cnt12.vhd(37) | Register bit cnt[2] is always 0, optimizing ... @W:MO160 : cnt12.vhd(37) | Register bit cnt[1] is always 0, optimizing ... @W:MO160 : cnt12.vhd(37) | Register bit cnt[0] is always 0, optimizing ... @W:MO160 : fifo_wrapper.vhd(129) | Register bit FIFO.read_counter[3] is always 0, optimizing ... @W:MO160 : fifo_wrapper.vhd(129) | Register bit FIFO.read_counter[2] is always 0, optimizing ... @W:MO160 : fifo_wrapper.vhd(129) | Register bit FIFO.read_counter[1] is always 0, optimizing ... @W:MO160 : fifo_wrapper.vhd(129) | Register bit FIFO.read_counter[0] is always 0, optimizing ... Encoding state machine current_state[0:6] (view:work.serialb_com(behave)) original code -> new code 0000001 -> 0000001 0000010 -> 0000010 0000100 -> 0000100 0001000 -> 0001000 0010000 -> 0010000 0100000 -> 0100000 1000000 -> 1000000 @N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L1_message_reg_0[0] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs @N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L1_message_reg_0[1] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs @N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L1_message_reg_0[2] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs @N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L1_message_reg_0[3] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs @N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L1_message_reg_0[11] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs @N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L2a_message_reg_3[2] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs @N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L2a_message_reg_3[3] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs @N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L2a_message_reg_3[4] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs @N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L2a_message_reg_3[5] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs @N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L2a_message_reg_3[6] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs @N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L2a_message_reg_3[7] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs @N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L2a_message_reg_3[11] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs @W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L1_state[1], because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L1_state[0] @W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L1_state[2], because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L1_state[0] @W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L1_state[3], because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L1_state[0] @W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L1_state[4], because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L1_state[0] @W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L1_state[5], because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L1_state[0] @W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L1_state[6], because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L1_state[0] @W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L1_state[7], because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L1_state[0] @W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L1_state[12], because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L1_state[0] @W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L2_state[8], because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L2_state[0] @W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L2_state[9], because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L2_state[0] @W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L2_state[10], because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L2_state[0] @W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L2_state[11], because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L2_state[0] @W:BN132 : addressed_msg_decoder.vhd(298) | Removing instance trigger_receiver_0.addressed_message_decoder.L2_state[12], because it is equivalent to instance trigger_receiver_0.addressed_message_decoder.L2_state[0] @N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L1_state[0] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs @N:BN362 : addressed_msg_decoder.vhd(298) | Removing sequential instance L2_state[0] in hierarchy view:work.addressed_message_decoder(arc) because there are no references to its outputs Encoding state machine current_state[0:8] (view:work.sequence_validator(behave)) original code -> new code 000000001 -> 000000001 000000010 -> 000000010 000000100 -> 000000100 000001000 -> 000001000 000010000 -> 000010000 000100000 -> 000100000 001000000 -> 001000000 010000000 -> 010000000 100000000 -> 100000000 @N: : phase_check.vhd(61) | Found counter in view:work.phase_check(behave) inst phase_cnt[4:0] @N: : counters.vhd(188) | Found counter in view:work.counters(arc) inst pp_Counter_i[15:0] @N: : counters.vhd(188) | Found counter in view:work.counters(arc) inst L2r_Counter_i[15:0] @N: : counters.vhd(188) | Found counter in view:work.counters(arc) inst L2a_Counter_i[15:0] @N: : counters.vhd(188) | Found counter in view:work.counters(arc) inst L1_msg_Counter_i[15:0] @N: : counters.vhd(188) | Found counter in view:work.counters(arc) inst L1_Counter_i[15:0] @N: : counters.vhd(188) | Found counter in view:work.counters(arc) inst L0_Counter_i[15:0] @N: : counters.vhd(142) | Found counter in view:work.counters(arc) inst seqErrorCnt_i[15:0] @N: : counters.vhd(142) | Found counter in view:work.counters(arc) inst sbError_Count[15:0] @N: : counters.vhd(142) | Found counter in view:work.counters(arc) inst msgErrorCnt_i[15:0] @N: : counters.vhd(142) | Found counter in view:work.counters(arc) inst dbError_Count[15:0] @N: : counters.vhd(169) | Found counter in view:work.counters(arc) inst Bunch_Counter_i[12:0] @N:FX404 : counters.vhd(255) | Found addmux in view:work.counters(arc) inst p_BCID_local\.BCID_Local_i_6[11:0] from un1_Bunch_Counter_i_1[12:1] @N:MF179 : counters.vhd(298) | Found 16 bit by 16 bit '==' comparator, 'p_timewindow\.un29_tw_counter' @N:MF179 : counters.vhd(305) | Found 16 bit by 16 bit '==' comparator, 'p_timewindow\.un37_tw_counter' @N:MF179 : counters.vhd(309) | Found 16 bit by 16 bit '==' comparator, 'p_timewindow\.un39_tw_counter' @N:MF179 : counters.vhd(312) | Found 16 bit by 16 bit '==' comparator, 'p_timewindow\.un42_tw_counter' @N:MF179 : counters.vhd(316) | Found 16 bit by 16 bit '==' comparator, 'p_timewindow\.un44_tw_counter' @N:MF179 : counters.vhd(319) | Found 16 bit by 16 bit '==' comparator, 'p_timewindow\.un46_tw_counter' @N:BN362 : addressed_msg_decoder.vhd(127) | Removing sequential instance addressed_message_decoder.current_state[0] in hierarchy view:work.trigger_receiver(arc) because there are no references to its outputs @N:BN362 : cmd_decoder.vhd(53) | Removing sequential instance RCU_DEC_0.U4_CMDDECODER.cmd_vector[5] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : coresf2config.vhd(237) | Removing sequential instance CoreSF2Config_0.paddr[14] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs Finished factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 156MB peak: 156MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 151MB peak: 158MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 149MB peak: 158MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 150MB peak: 158MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 150MB peak: 158MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 149MB peak: 158MB) @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[0] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[1] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[2] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[3] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[4] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[5] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[6] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[7] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[8] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[9] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[10] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[11] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[12] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[13] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[14] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[15] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[16] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[17] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[18] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cnt20.vhd(38) | Removing sequential instance RCU_DEC_0.U6_ABSCNT.U1_DSTBCNTA.cnt[19] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs @N:BN362 : cmd_decoder.vhd(53) | Removing sequential instance RCU_DEC_0.U4_CMDDECODER.cmd_vector[4] in hierarchy view:work.Trigger_receiver_v1_7(rtl) because there are no references to its outputs Finished preparing to map (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 150MB peak: 158MB) Finished technology mapping (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 178MB peak: 227MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:16s -6.85ns 1701 / 895 2 0h:00m:16s -6.89ns 1703 / 895 ------------------------------------------------------------ @N:FX271 : coresf2reset.vhd(732) | Instance "CoreSF2Reset_0.count[1]" with 4 loads replicated 1 times to improve timing @N:FX271 : coresf2reset.vhd(732) | Instance "CoreSF2Reset_0.count[0]" with 5 loads replicated 1 times to improve timing Timing driven replication report Added 2 Registers via timing driven replication Added 1 LUTs via timing driven replication Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:18s -1.00ns 1705 / 897 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:18s -1.00ns 1705 / 897 ------------------------------------------------------------ @N:FP130 : | Promoting Net clk_40_c on CLKINT I_246 @N:FP130 : | Promoting Net CoreSF2Config_0_APB_S_PRESET_N on CLKINT I_247 @N:FP130 : | Promoting Net CoreSF2Reset_0.sm0_areset_n_rcosc on CLKINT I_248 @N:FP130 : | Promoting Net Trigger_receiver_v1_7_MSS_0_MSS_RESET_N_M2F on CLKINT I_249 @N:FP130 : | Promoting Net CoreSF2Config_0_APB_S_PCLK on CLKINT I_250 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:19s; CPU Time elapsed 0h:00m:19s; Memory used current: 165MB peak: 227MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:19s; Memory used current: 166MB peak: 227MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 2 non-gated/non-generated clock tree(s) driving 825 clock pin(s) of sequential element(s) 4 gated/generated clock tree(s) driving 72 clock pin(s) of sequential element(s) 0 instances converted, 72 sequential instances remain driven by gated/generated clocks ====================================== Non-Gated/Non-Generated Clocks ======================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------------------------- ClockId0005 FCCC_0.GL2_INST CLKINT 791 trigger_receiver_0.trigger_input_mask ClockId0006 FCCC_2.GL0_INST CLKINT 34 CoreSF2Reset_0.count_fast[0] ============================================================================================================= ====================================================================================================================== Gated/Generated Clocks ====================================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST MSS_050 56 CoreSF2Config_0.INIT_DONE_q3 Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements ClockId0002 ttc_0.clk_div.change_ph_3 SLE 9 ttc_0.ch_b_det.count[4] No generated or derived clock directive on output of sequential instance ClockId0003 ttc_0.cdr_top.cdr.clk_out CFG2 6 ttc_0.cdr_top.cdr.data_out Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements ClockId0004 ttc_0.cdr_top.cdr.input_d CFG2 1 ttc_0.cdr_top.cdr.output_e_del Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements ==================================================================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Writing Analyst data base C:\Actelprj\System_w_Linux_11_2\synthesis\Trigger_receiver_v1_7.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:22s; CPU Time elapsed 0h:00m:22s; Memory used current: 160MB peak: 227MB) Writing EDIF Netlist and constraint files H-2013.03M-SP1-1 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:23s; CPU Time elapsed 0h:00m:23s; Memory used current: 161MB peak: 227MB) @W:MT246 : trigger_receiver_v1_7.vhd(1241) | Blackbox SYSRESET is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : trigger_receiver_v1_7_mss.vhd(2061) | Blackbox MSS_050 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : trigger_receiver_v1_7_osc_0_osc.vhd(36) | Blackbox XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : trigger_receiver_v1_7_fccc_2_fccc.vhd(105) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) Found clock MAC_MII_RX_CLK with period 40.00ns Found clock MAC_MII_TX_CLK with period 40.00ns @W:MT420 : | Found inferred clock clk_div|change_ph_3_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:ttc_0.clk_div.change_ph_3" @W:MT420 : | Found inferred clock Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:Trigger_receiver_v1_7_MSS_0.FIC_2_APB_M_PCLK" @W:MT420 : | Found inferred clock Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FCCC_2.GL0_net" Found clock GL2_net_inferred_clock with period 25.00ns ##### START OF TIMING REPORT #####[ # Timing Report written on Wed Nov 27 17:14:43 2013 # Top view: Trigger_receiver_v1_7 Requested Frequency: 25.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\Actelprj\System_w_Linux_11_2\constraint\Trigger_receiver_1_7_synplify.sdc @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 1.905 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------------------------------- GL2_net_inferred_clock 40.0 MHz 78.3 MHz 25.000 12.772 10.861 declared Inferred_clkgrp_4 MAC_MII_RX_CLK 25.0 MHz NA 40.000 NA NA declared MAC_Clocks MAC_MII_TX_CLK 25.0 MHz NA 40.000 NA NA declared MAC_Clocks Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock 100.0 MHz 347.6 MHz 10.000 2.877 7.123 inferred Inferred_clkgroup_1 Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 161.5 MHz 10.000 6.190 1.905 inferred Inferred_clkgroup_2 clk_div|change_ph_3_inferred_clock 100.0 MHz 362.9 MHz 10.000 2.756 3.972 inferred Inferred_clkgroup_0 System 100.0 MHz 175.4 MHz 10.000 5.701 4.299 system system_clkgroup ================================================================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 10.000 4.299 | No paths - | No paths - | No paths - System GL2_net_inferred_clock | 25.000 17.752 | No paths - | No paths - | No paths - System clk_div|change_ph_3_inferred_clock | 10.000 5.373 | No paths - | 10.000 8.868 | No paths - System Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock | 10.000 5.512 | No paths - | No paths - | No paths - GL2_net_inferred_clock System | 25.000 22.000 | No paths - | No paths - | No paths - GL2_net_inferred_clock GL2_net_inferred_clock | 25.000 12.228 | 25.000 23.801 | 12.500 11.142 | 12.500 10.862 clk_div|change_ph_3_inferred_clock System | 10.000 8.972 | No paths - | No paths - | No paths - clk_div|change_ph_3_inferred_clock GL2_net_inferred_clock | No paths - | No paths - | Diff grp - | No paths - clk_div|change_ph_3_inferred_clock clk_div|change_ph_3_inferred_clock | 10.000 7.244 | No paths - | No paths - | 5.000 3.972 Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock | 10.000 7.123 | No paths - | No paths - | No paths - Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock System | 10.000 7.674 | No paths - | No paths - | 10.000 7.466 Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock | 10.000 5.724 | No paths - | 5.000 2.541 | 5.000 1.905 ================================================================================================================================================================================================================ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: GL2_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------ trigger_receiver_0.L1_line_decoder.shiftreg[2] GL2_net_inferred_clock SLE Q shiftreg[2] 0.108 10.861 trigger_receiver_0.L1_line_decoder.shiftreg[0] GL2_net_inferred_clock SLE Q shiftreg[0] 0.108 10.957 trigger_receiver_0.L1_line_decoder.shiftreg[1] GL2_net_inferred_clock SLE Q shiftreg[1] 0.087 11.065 trigger_receiver_0.RCU_bus_communication.input_enable_i GL2_net_inferred_clock SLE Q input_enable 0.108 11.142 trigger_receiver_0.serialb_decoder.serialBchannelR GL2_net_inferred_clock SLE Q serialBchannelR 0.087 11.472 trigger_receiver_0.serialb_decoder.received_word[11] GL2_net_inferred_clock SLE Q received_data[11] 0.108 12.228 trigger_receiver_0.serialb_decoder.received_word[13] GL2_net_inferred_clock SLE Q received_data[13] 0.108 12.279 trigger_receiver_0.serialb_decoder.received_word[10] GL2_net_inferred_clock SLE Q received_data[10] 0.108 12.328 trigger_receiver_0.serialb_decoder.received_word[34] GL2_net_inferred_clock SLE Q received_data[34] 0.108 12.392 trigger_receiver_0.serialb_decoder.received_word[8] GL2_net_inferred_clock SLE Q received_data[8] 0.108 12.395 ================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------- trigger_receiver_0.L1_line_decoder.L0 GL2_net_inferred_clock SLE D L0_2 12.245 10.861 trigger_receiver_0.L1_line_decoder.L1a GL2_net_inferred_clock SLE D N_502_i_0 12.245 10.861 trigger_receiver_0.serialb_decoder.serialBchannelR GL2_net_inferred_clock SLE D serialBchannelR_0 12.245 11.142 trigger_receiver_0.L1_line_decoder.shiftreg[0] GL2_net_inferred_clock SLE D shiftreg_0[0] 12.245 11.188 trigger_receiver_0.serialb_decoder.serialBchannelRR GL2_net_inferred_clock SLE D serialBchannelR 12.245 11.472 trigger_receiver_0.addressed_message_decoder.msg_error GL2_net_inferred_clock SLE D msg_error_7 24.745 12.228 trigger_receiver_0.addressed_message_decoder.TTCrx_addr_error GL2_net_inferred_clock SLE EN un1_ttcrx_addr_error2_i_0 24.663 12.498 trigger_receiver_0.addressed_message_decoder.current_state[7] GL2_net_inferred_clock SLE D current_state_3[7] 24.745 12.646 trigger_receiver_0.addressed_message_decoder.current_state[11] GL2_net_inferred_clock SLE D current_state_3[11] 24.745 12.646 trigger_receiver_0.addressed_message_decoder.current_state[8] GL2_net_inferred_clock SLE D current_state_3[8] 24.745 12.788 ================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 12.500 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 12.245 - Propagation time: 1.383 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 10.861 Number of logic level(s): 1 Starting point: trigger_receiver_0.L1_line_decoder.shiftreg[2] / Q Ending point: trigger_receiver_0.L1_line_decoder.L1a / D The start point is clocked by GL2_net_inferred_clock [falling] on pin CLK The end point is clocked by GL2_net_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------- trigger_receiver_0.L1_line_decoder.shiftreg[2] SLE Q Out 0.108 0.108 - shiftreg[2] Net - - 0.674 - 2 trigger_receiver_0.L1_line_decoder.L1a_RNO CFG4 D In - 0.783 - trigger_receiver_0.L1_line_decoder.L1a_RNO CFG4 Y Out 0.442 1.225 - N_502_i_0 Net - - 0.159 - 1 trigger_receiver_0.L1_line_decoder.L1a SLE D In - 1.383 - ============================================================================================================= Total path delay (propagation time + setup) of 1.639 is 0.806(49.2%) logic and 0.833(50.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------- CoreSF2Reset_0.count[2] Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE Q count[2] 0.108 7.123 CoreSF2Reset_0.count[3] Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE Q count[3] 0.108 7.127 CoreSF2Reset_0.count[5] Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE Q count[5] 0.087 7.141 CoreSF2Reset_0.count[7] Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE Q count[7] 0.108 7.143 CoreSF2Reset_0.count[0] Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE Q count[0] 0.087 7.351 CoreSF2Reset_0.count[6] Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE Q count[6] 0.108 7.360 CoreSF2Reset_0.count[4] Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE Q count[4] 0.108 7.419 CoreSF2Reset_0.count[1] Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE Q count[1] 0.108 7.431 CoreSF2Reset_0.count[8] Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE Q count[8] 0.108 7.433 CoreSF2Reset_0.count[9] Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE Q count[9] 0.108 7.464 ======================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------- CoreSF2Reset_0.count_130us_0 Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE EN un14_count 9.662 7.123 CoreSF2Reset_0.count[13] Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE D count_s[13] 9.745 7.127 CoreSF2Reset_0.count_ddr_0 Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE EN un18_count 9.662 7.141 CoreSF2Reset_0.count[12] Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE D count_s[12] 9.745 7.143 CoreSF2Reset_0.count[11] Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE D count_s[11] 9.745 7.159 CoreSF2Reset_0.count[10] Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE D count_s[10] 9.745 7.175 CoreSF2Reset_0.count[9] Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE D count_s[9] 9.745 7.192 CoreSF2Reset_0.count[8] Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE D count_s[8] 9.745 7.386 CoreSF2Reset_0.count[7] Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE D count_s[7] 9.745 7.403 CoreSF2Reset_0.count[6] Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock SLE D count_s[6] 9.745 7.419 ================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.338 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.662 - Propagation time: 2.540 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.123 Number of logic level(s): 2 Starting point: CoreSF2Reset_0.count[2] / Q Ending point: CoreSF2Reset_0.count_130us_0 / EN The start point is clocked by Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock [rising] on pin CLK The end point is clocked by Trigger_receiver_v1_7_FCCC_2_FCCC|GL0_net_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------- CoreSF2Reset_0.count[2] SLE Q Out 0.108 0.108 - count[2] Net - - 0.778 - 4 CoreSF2Reset_0.un14_count_7 CFG4 D In - 0.886 - CoreSF2Reset_0.un14_count_7 CFG4 Y Out 0.470 1.356 - un14_count_7 Net - - 0.556 - 1 CoreSF2Reset_0.un14_count CFG4 D In - 1.911 - CoreSF2Reset_0.un14_count CFG4 Y Out 0.470 2.381 - un14_count Net - - 0.159 - 1 CoreSF2Reset_0.count_130us_0 SLE EN In - 2.540 - =========================================================================================== Total path delay (propagation time + setup) of 2.877 is 1.385(48.1%) logic and 1.492(51.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreSF2Config_0.psel Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q psel 0.087 1.905 CoreSF2Config_0.state[1] Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q state[1] 0.087 2.541 CoreSF2Config_0.paddr[15] Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q paddr[15] 0.108 3.402 CoreSF2Config_0.paddr[13] Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q paddr[13] 0.108 3.510 CoreSF2Config_0.state[0] Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q state[0] 0.087 3.556 CoreSF2Config_0.paddr[12] Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q paddr[12] 0.108 3.642 CoreSF2Config_0.control_reg_1 Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q CoreSF2Config_0_CONFIG_DONE 0.087 6.337 CoreSF2Config_0.control_reg_2 Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q CoreSF2Config_0_CLR_INIT_DONE 0.087 6.470 CoreSF2Config_0.INIT_DONE_q2 Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q INIT_DONE_q2 0.087 7.080 CoreSF2Config_0.INIT_DONE_q3 Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q INIT_DONE_q3 0.108 8.601 ==================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreSF2Config_0.state[1] Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D state_ns[1] 4.745 1.905 CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[0] Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[0] 4.745 1.950 CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[1] Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[1] 4.745 2.037 CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[2] Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[2] 4.745 2.037 CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[3] Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[3] 4.745 2.037 CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[4] Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[4] 4.745 2.037 CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[5] Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[5] 4.745 2.037 CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[6] Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[6] 4.745 2.037 CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[7] Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[7] 4.745 2.037 CoreSF2Config_0.FIC_2_APB_M_PRDATA_0[8] Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[8] 4.745 2.037 ============================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.745 - Propagation time: 2.840 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 1.905 Number of logic level(s): 2 Starting point: CoreSF2Config_0.psel / Q Ending point: CoreSF2Config_0.state[1] / D The start point is clocked by Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock [falling] on pin CLK The end point is clocked by Trigger_receiver_v1_7_MSS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- CoreSF2Config_0.psel SLE Q Out 0.087 0.087 - psel Net - - 0.814 - 5 CoreSF2Config_0.MDDR_PSEL_0_0_a2 CFG4 D In - 0.902 - CoreSF2Config_0.MDDR_PSEL_0_0_a2 CFG4 Y Out 0.428 1.330 - CoreSF2Config_0_MDDR_APBmslave_PSELx Net - - 1.142 - 19 CoreSF2Config_0.state_ns_0_0[1] CFG3 C In - 2.472 - CoreSF2Config_0.state_ns_0_0[1] CFG3 Y Out 0.209 2.681 - state_ns[1] Net - - 0.159 - 1 CoreSF2Config_0.state[1] SLE D In - 2.840 - =================================================================================================== Total path delay (propagation time + setup) of 3.095 is 0.980(31.7%) logic and 2.115(68.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: clk_div|change_ph_3_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------- ttc_0.demultiplexAB.data_80_delay clk_div|change_ph_3_inferred_clock SLE Q data_80_delay 0.087 3.972 ttc_0.demultiplexAB.ch_a clk_div|change_ph_3_inferred_clock SLE Q ttc_0_ch_a 0.108 7.244 ttc_0.ch_b_det.count[1] clk_div|change_ph_3_inferred_clock SLE Q count[1] 0.108 7.577 ttc_0.ch_b_det.count[3] clk_div|change_ph_3_inferred_clock SLE Q count[3] 0.087 7.618 ttc_0.ch_b_det.count[0] clk_div|change_ph_3_inferred_clock SLE Q count[0] 0.108 7.856 ttc_0.ch_b_det.count[2] clk_div|change_ph_3_inferred_clock SLE Q count[2] 0.108 8.470 ttc_0.ch_b_det.count[4] clk_div|change_ph_3_inferred_clock SLE Q count[4] 0.108 8.573 ttc_0.ch_b_det.ch_b_det clk_div|change_ph_3_inferred_clock SLE Q ch_b_det_i 0.087 8.972 ================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------- ttc_0.demultiplexAB.ch_b clk_div|change_ph_3_inferred_clock SLE D data_80_delay 4.745 3.972 ttc_0.ch_b_det.count[0] clk_div|change_ph_3_inferred_clock SLE SLn N_1572_i 9.662 7.244 ttc_0.ch_b_det.count[1] clk_div|change_ph_3_inferred_clock SLE SLn N_1572_i 9.662 7.244 ttc_0.ch_b_det.count[2] clk_div|change_ph_3_inferred_clock SLE SLn N_1572_i 9.662 7.244 ttc_0.ch_b_det.count[3] clk_div|change_ph_3_inferred_clock SLE SLn N_1572_i 9.662 7.244 ttc_0.ch_b_det.count[4] clk_div|change_ph_3_inferred_clock SLE SLn N_1572_i 9.662 7.244 ttc_0.ch_b_det.count[0] clk_div|change_ph_3_inferred_clock SLE EN count_or[4] 9.662 7.288 ttc_0.ch_b_det.count[1] clk_div|change_ph_3_inferred_clock SLE EN count_or[4] 9.662 7.288 ttc_0.ch_b_det.count[2] clk_div|change_ph_3_inferred_clock SLE EN count_or[4] 9.662 7.288 ttc_0.ch_b_det.count[3] clk_div|change_ph_3_inferred_clock SLE EN count_or[4] 9.662 7.288 ========================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.745 - Propagation time: 0.773 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 3.972 Number of logic level(s): 0 Starting point: ttc_0.demultiplexAB.data_80_delay / Q Ending point: ttc_0.demultiplexAB.ch_b / D The start point is clocked by clk_div|change_ph_3_inferred_clock [falling] on pin CLK The end point is clocked by clk_div|change_ph_3_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------ ttc_0.demultiplexAB.data_80_delay SLE Q Out 0.087 0.087 - data_80_delay Net - - 0.685 - 1 ttc_0.demultiplexAB.ch_b SLE D In - 0.773 - ================================================================================================ Total path delay (propagation time + setup) of 1.028 is 0.343(33.3%) logic and 0.685(66.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 F_HM0_ADDR[12] RCU_DEC_0_rcu_add[8] 0.000 4.299 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 F_HM0_ADDR[13] RCU_DEC_0_rcu_add[9] 0.000 4.543 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 F_HM0_ADDR[14] RCU_DEC_0_rcu_add[10] 0.000 4.625 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 F_HM0_ADDR[15] RCU_DEC_0_rcu_add[11] 0.000 4.668 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 F_HM0_ADDR[19] RCU_DEC_0_rcu_add[15] 0.000 4.875 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 F_HM0_ADDR[17] RCU_DEC_0_rcu_add[13] 0.000 4.925 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 F_HM0_ADDR[31] Trigger_receiver_v1_7_MSS_0_FIC_0_APB_MASTER_PADDR[31] 0.000 5.371 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 FPGA_RESET_N FPGA_RESET_N 0.000 5.373 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 F_HM0_ADDR[29] Trigger_receiver_v1_7_MSS_0_FIC_0_APB_MASTER_PADDR[29] 0.000 5.414 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 PER2_FABRIC_PWRITE Trigger_receiver_v1_7_MSS_0_FIC_2_APB_MASTER_PWRITE 0.000 5.512 ============================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 F_HM0_RDATA[0] Trigger_receiver_v1_7_MSS_0_FIC_0_APB_MASTER_PRDATA[0] 10.000 4.299 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 F_HM0_RDATA[2] Trigger_receiver_v1_7_MSS_0_FIC_0_APB_MASTER_PRDATA[2] 10.000 4.299 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 F_HM0_RDATA[5] Trigger_receiver_v1_7_MSS_0_FIC_0_APB_MASTER_PRDATA[5] 10.000 4.299 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 F_HM0_RDATA[6] Trigger_receiver_v1_7_MSS_0_FIC_0_APB_MASTER_PRDATA[6] 10.000 4.299 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 F_HM0_RDATA[7] Trigger_receiver_v1_7_MSS_0_FIC_0_APB_MASTER_PRDATA[7] 10.000 4.299 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 F_HM0_RDATA[9] Trigger_receiver_v1_7_MSS_0_FIC_0_APB_MASTER_PRDATA[9] 10.000 4.299 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 F_HM0_RDATA[17] Trigger_receiver_v1_7_MSS_0_FIC_0_APB_MASTER_PRDATA[17] 10.000 4.299 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 F_HM0_RDATA[18] Trigger_receiver_v1_7_MSS_0_FIC_0_APB_MASTER_PRDATA[18] 10.000 4.299 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 F_HM0_RDATA[19] Trigger_receiver_v1_7_MSS_0_FIC_0_APB_MASTER_PRDATA[19] 10.000 4.299 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST System MSS_050 F_HM0_RDATA[24] Trigger_receiver_v1_7_MSS_0_FIC_0_APB_MASTER_PRDATA[24] 10.000 4.299 =========================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 5.701 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 4.299 Number of logic level(s): 4 Starting point: Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[12] Ending point: Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[7] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------- Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST MSS_050 F_HM0_ADDR[12] Out 0.000 0.000 - RCU_DEC_0_rcu_add[8] Net - - 1.123 - 2 RCU_DEC_0.rcu_dout_23_0_0_a4_1 CFG4 D In - 1.123 - RCU_DEC_0.rcu_dout_23_0_0_a4_1 CFG4 Y Out 0.470 1.593 - N_692 Net - - 0.630 - 2 RCU_DEC_0.U4_CMDDECODER.cmd_vector_11_0_a2_0_a4_1_1_RNIUDAC1_0[5] CFG4 D In - 2.223 - RCU_DEC_0.U4_CMDDECODER.cmd_vector_11_0_a2_0_a4_1_1_RNIUDAC1_0[5] CFG4 Y Out 0.470 2.692 - N_695 Net - - 1.007 - 25 RCU_DEC_0.U5_RCUREG.dout_RNI01KS1[7] CFG4 B In - 3.700 - RCU_DEC_0.U5_RCUREG.dout_RNI01KS1[7] CFG4 Y Out 0.164 3.864 - RCU_DEC_0_dcs_busBdata_in[7] Net - - 0.556 - 1 CoreAPB3_0.CAPB3OOl1.PRData[7] CFG3 B In - 4.420 - CoreAPB3_0.CAPB3OOl1.PRData[7] CFG3 Y Out 0.164 4.584 - Trigger_receiver_v1_7_MSS_0_FIC_0_APB_MASTER_PRDATA[7] Net - - 1.117 - 1 Trigger_receiver_v1_7_MSS_0.MSS_ADLIB_INST MSS_050 F_HM0_RDATA[7] In - 5.701 - ============================================================================================================================================= Total path delay (propagation time + setup) of 5.701 is 1.268(22.2%) logic and 4.433(77.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report for Trigger_receiver_v1_7 Mapping to part: m2s050t_esfbga896std Cell usage: BUFD 35 uses CCC 3 uses CLKINT 8 uses MSS_050 1 use OR2 1 use XTLOSC 1 use CFG1 19 uses CFG2 320 uses CFG3 393 uses CFG4 635 uses Carry primitives used for arithmetic functions: ARI1 316 uses Sequential Cells: SLE 898 uses DSP Blocks: 0 I/O ports: 87 I/O primitives: 84 BIBUF 23 uses INBUF 14 uses INBUF_DIFF 1 use OUTBUF 42 uses OUTBUF_DIFF 1 use SYSRESET 1 use TRIBUFF 2 uses Global Clock Buffers: 8 Total LUTs: 1683 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:25s; CPU Time elapsed 0h:00m:24s; Memory used current: 55MB peak: 227MB) Process took 0h:00m:25s realtime, 0h:00m:24s cputime # Wed Nov 27 17:14:44 2013 ###########################################################]