Synopsys VHDL Compiler, version comp201303rcp1, Build 114R, built May 21 2013
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

@N:CD720 : std.vhd(146) | Setting time resolution to ns
@N: : Trigger_receiver_v1_7.vhd(20) | Top entity is set to Trigger_receiver_v1_7.
VHDL syntax check successful!
@N:CD231 : std1164.vhd(913) | Using onehot encoding for type mvl9plus ('U'="1000000000")
@N:CD630 : Trigger_receiver_v1_7.vhd(20) | Synthesizing work.trigger_receiver_v1_7.rtl 
@N:CD630 : smartfusion2.vhd(492) | Synthesizing smartfusion2.inbuf_diff.syn_black_box 
Post processing for smartfusion2.inbuf_diff.syn_black_box
@N:CD630 : ttc.vhd(5) | Synthesizing work.ttc.connect 
@N:CD630 : ch_b_det.vhd(41) | Synthesizing work.ch_b_det.behavioral 
Post processing for work.ch_b_det.behavioral
@A:CL282 : ch_b_det.vhd(59) | Feedback mux created for signal count[4:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@N:CD630 : demultiplexAB.vhd(39) | Synthesizing work.demultiplexab.behavioral 
Post processing for work.demultiplexab.behavioral
@N:CD630 : clk_div.vhd(39) | Synthesizing work.clk_div.behavioral 
Post processing for work.clk_div.behavioral
@N:CD630 : cdr_top.vhd(43) | Synthesizing work.cdr_top.behave 
@N:CD630 : hp_cdr.vhd(7) | Synthesizing work.hp_cdr.hp_fig2 
Post processing for work.hp_cdr.hp_fig2
@W:CL111 : hp_cdr.vhd(29) | All reachable assignments to err_det assign '0'; register removed by optimization
@N:CD630 : smartfusion2.vhd(349) | Synthesizing smartfusion2.bufd.syn_black_box 
Post processing for smartfusion2.bufd.syn_black_box
Post processing for work.cdr_top.behave
Post processing for work.ttc.connect
@N:CD630 : Trigger_receiver_v1_7_MSS.vhd(17) | Synthesizing work.trigger_receiver_v1_7_mss.rtl 
@N:CD630 : smartfusion2.vhd(403) | Synthesizing smartfusion2.inbuf.syn_black_box 
Post processing for smartfusion2.inbuf.syn_black_box
@N:CD630 : smartfusion2.vhd(423) | Synthesizing smartfusion2.tribuff.syn_black_box 
Post processing for smartfusion2.tribuff.syn_black_box
@N:CD630 : Trigger_receiver_v1_7_MSS_tmp_syn.vhd(10) | Synthesizing work.mss_050.def_arch 
Post processing for work.mss_050.def_arch
Post processing for work.trigger_receiver_v1_7_mss.rtl
@N:CD630 : trigger_receiver.vhd(43) | Synthesizing work.trigger_receiver.arc 
@W:CD326 : trigger_receiver.vhd(306) | Port l2_extendedlatency of entity work.rcu_com_release is unconnected
@N:CD630 : counters.vhd(44) | Synthesizing work.counters.arc 
Post processing for work.counters.arc
@N:CD630 : fifo_wrapper.vhd(41) | Synthesizing work.fifo_wrapper.behave 
@N:CD364 : fifo_wrapper.vhd(163) | Removed redundant assignment
@N:CD630 : ms_event_fifo.vhd(19) | Synthesizing work.ms_event_fifo.rtl 
@N:CD630 : COREFIFO.vhd(13) | Synthesizing corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_corefifo.cfifol 
@W:CD638 : COREFIFO.vhd(245) | Signal cfifoo1l is undriven 
@W:CD638 : COREFIFO.vhd(247) | Signal cfifol1l is undriven 
@W:CD638 : COREFIFO.vhd(253) | Signal cfifol0l is undriven 
@W:CD638 : COREFIFO.vhd(259) | Signal cfifoi0l is undriven 
@W:CD638 : COREFIFO.vhd(285) | Signal cfifoi0i is undriven 
@N:CD630 : ms_event_fifo_ms_event_fifo_0_ram_wrapper.vhd(10) | Synthesizing corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_ram_wrapper.generated 
@N:CD630 : ms_event_fifo_ms_event_fifo_0_USRAM_top.vhd(8) | Synthesizing corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_usram_top.def_arch 
@N:CD630 : smartfusion2.vhd(620) | Synthesizing smartfusion2.ram64x18.syn_black_box 
Post processing for smartfusion2.ram64x18.syn_black_box
@N:CD630 : smartfusion2.vhd(575) | Synthesizing smartfusion2.vcc.syn_black_box 
Post processing for smartfusion2.vcc.syn_black_box
@N:CD630 : smartfusion2.vhd(569) | Synthesizing smartfusion2.gnd.syn_black_box 
Post processing for smartfusion2.gnd.syn_black_box
@N:CD630 : smartfusion2.vhd(342) | Synthesizing smartfusion2.inv.syn_black_box 
Post processing for smartfusion2.inv.syn_black_box
Post processing for corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_usram_top.def_arch
Post processing for corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_ram_wrapper.generated
@N:CD630 : fifocore_sync_scntr.vhd(13) | Synthesizing corefifo_obf_lib.cfifolil.cfifol 
@W:CD638 : fifocore_sync_scntr.vhd(108) | Signal cfifooiil is undriven 
Post processing for corefifo_obf_lib.cfifolil.cfifol
@W:CL169 : fifocore_sync_scntr.vhd(245) | Pruning register CFIFOL0il  
@W:CL169 : fifocore_sync_scntr.vhd(237) | Pruning register CFIFOl1OL  
@W:CL111 : fifocore_sync_scntr.vhd(279) | All reachable assignments to CFIFOoOLl assign '0'; register removed by optimization
@W:CL111 : fifocore_sync_scntr.vhd(279) | All reachable assignments to CFIFOLOll assign '0'; register removed by optimization
@W:CL111 : fifocore_sync_scntr.vhd(253) | All reachable assignments to CFIFOi1OL assign '0'; register removed by optimization
@W:CL111 : fifocore_sync_scntr.vhd(253) | All reachable assignments to CFIFOO1oL assign '0'; register removed by optimization
Post processing for corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_corefifo.cfifol
Post processing for work.ms_event_fifo.rtl
Post processing for work.fifo_wrapper.behave
@N:CD630 : phase_check.vhd(37) | Synthesizing work.phase_check.behave 
Post processing for work.phase_check.behave
@N:CD630 : sequence_validator.vhd(40) | Synthesizing work.sequence_validator.behave 
@N:CD231 : sequence_validator.vhd(93) | Using onehot encoding for type state (s_idle="100000000")
@W:CD604 : sequence_validator.vhd(253) | OTHERS clause is not synthesized 
@W:CD434 : sequence_validator.vhd(189) | Signal timeout_counter in the sensitivity list is not used in the process
Post processing for work.sequence_validator.behave
@W:CL169 : sequence_validator.vhd(261) | Pruning register timeout_counter(3 downto 0)  
@W:CL169 : sequence_validator.vhd(261) | Pruning register pre_pulseR  
@W:CL190 : sequence_validator.vhd(261) | Optimizing register bit prepulse_error to a constant 0
@W:CL169 : sequence_validator.vhd(261) | Pruning register prepulse_error  
@N:CD630 : L1_line_decoder.vhd(37) | Synthesizing work.l1_line_decoder.behave 
Post processing for work.l1_line_decoder.behave
@N:CD630 : addressed_msg_decoder.vhd(41) | Synthesizing work.addressed_message_decoder.arc 
@N:CD231 : addressed_msg_decoder.vhd(68) | Using onehot encoding for type state (s_idle="10000000000000")
Post processing for work.addressed_message_decoder.arc
@N:CD630 : broadcast_msg_decoder.vhd(41) | Synthesizing work.broadcast_message_decoder.behave 
Post processing for work.broadcast_message_decoder.behave
@N:CD630 : hamming_decoder.vhd(39) | Synthesizing work.hamming_decoder.behave 
Post processing for work.hamming_decoder.behave
@N:CD630 : serialb_com.vhd(39) | Synthesizing work.serialb_com.behave 
@N:CD231 : serialb_com.vhd(55) | Using onehot encoding for type state (s_idle="1000000")
@W:CD604 : serialb_com.vhd(148) | OTHERS clause is not synthesized 
Post processing for work.serialb_com.behave
@N:CD630 : rcu_com_release.vhd(41) | Synthesizing work.rcu_com_release.arc 
Post processing for work.rcu_com_release.arc
Post processing for work.trigger_receiver.arc
@N:CD630 : smartfusion2.vhd(779) | Synthesizing smartfusion2.sysreset.syn_black_box 
Post processing for smartfusion2.sysreset.syn_black_box
@N:CD630 : rcu_dec.vhd(64) | Synthesizing work.rcu_dec.a_rcudec 
@W:CD638 : rcu_dec.vhd(449) | Signal d_siu_rst is undriven 
@N:CD630 : abs_cnt.vhd(27) | Synthesizing work.abs_cnt.a_abscnt 
@N:CD630 : cnt12.vhd(19) | Synthesizing work.cnt12.a_cnt12 
Post processing for work.cnt12.a_cnt12
@N:CD630 : posdge_pulse.vhd(20) | Synthesizing work.posedge_pulse.a_posedge_pulse 
Post processing for work.posedge_pulse.a_posedge_pulse
@N:CD630 : cnt20.vhd(19) | Synthesizing work.cnt20.a_cnt20 
Post processing for work.cnt20.a_cnt20
Post processing for work.abs_cnt.a_abscnt
@N:CD630 : rcu_reg.vhd(62) | Synthesizing work.rcu_reg.a_rcureg 
@W:CD434 : rcu_reg.vhd(203) | Signal clk in the sensitivity list is not used in the process
@W:CD434 : rcu_reg.vhd(265) | Signal rst in the sensitivity list is not used in the process
Post processing for work.rcu_reg.a_rcureg
@W:CL117 : rcu_reg.vhd(205) | Latch generated from process for signal st_meb_full; possible missing assignment in an if or case statement.
@N:CD630 : cmd_decoder.vhd(21) | Synthesizing work.cmd_decoder.a_cmddecoder 
Post processing for work.cmd_decoder.a_cmddecoder
@N:CD630 : addr_decoder.vhd(23) | Synthesizing work.addr_decoder.a_addrdecoder 
Post processing for work.addr_decoder.a_addrdecoder
@N:CD630 : arbit.vhd(15) | Synthesizing work.arbit.a_arbit 
@N:CD233 : arbit.vhd(36) | Using sequential encoding for type sm
@W:CD604 : arbit.vhd(110) | OTHERS clause is not synthesized 
@W:CD604 : arbit.vhd(139) | OTHERS clause is not synthesized 
Post processing for work.arbit.a_arbit
@N:CD630 : mux_arbit.vhd(20) | Synthesizing work.mux_arbit.a_muxarbit 
Post processing for work.mux_arbit.a_muxarbit
@W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal siu_dout(31 downto 0); possible missing assignment in an if or case statement.
@W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal rcu_data(31 downto 0); possible missing assignment in an if or case statement.
@W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal dcs_dout(31 downto 0); possible missing assignment in an if or case statement.
@W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal rcu_add(15 downto 0); possible missing assignment in an if or case statement.
@W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal rcu_we; possible missing assignment in an if or case statement.
Post processing for work.rcu_dec.a_rcudec
@N:CD630 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(8) | Synthesizing work.trigger_receiver_v1_7_osc_0_osc.def_arch 
@N:CD630 : osc_comps.vhd(19) | Synthesizing work.rcosc_25_50mhz.def_arch 
Post processing for work.rcosc_25_50mhz.def_arch
Post processing for work.trigger_receiver_v1_7_osc_0_osc.def_arch
@W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(16) | XTLOSC_O2F is not assigned a value (floating) -- simulation mismatch possible. 
@W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(15) | XTLOSC_CCC is not assigned a value (floating) -- simulation mismatch possible. 
@W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(14) | RCOSC_1MHZ_O2F is not assigned a value (floating) -- simulation mismatch possible. 
@W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(13) | RCOSC_1MHZ_CCC is not assigned a value (floating) -- simulation mismatch possible. 
@W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(12) | RCOSC_25_50MHZ_O2F is not assigned a value (floating) -- simulation mismatch possible. 
@N:CD630 : smartfusion2.vhd(207) | Synthesizing smartfusion2.or2.syn_black_box 
Post processing for smartfusion2.or2.syn_black_box
@N:CD630 : led_blink.vhd(24) | Synthesizing work.led_blink.cnt 
@W:CG296 : led_blink.vhd(42) | Incomplete sensitivity list - assuming completeness
@W:CG290 : led_blink.vhd(46) | Referenced variable start is not in sensitivity list
Post processing for work.led_blink.cnt
@A:CL282 : led_blink.vhd(44) | Feedback mux created for signal start -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@W:CL113 : led_blink.vhd(44) | Feedback mux created for signal count[15:0].
@N:CD630 : Trigger_receiver_v1_7_FCCC_1_FCCC.vhd(8) | Synthesizing work.trigger_receiver_v1_7_fccc_1_fccc.def_arch 
@N:CD630 : smartfusion2.vhd(787) | Synthesizing smartfusion2.ccc.syn_black_box 
Post processing for smartfusion2.ccc.syn_black_box
@N:CD630 : smartfusion2.vhd(562) | Synthesizing smartfusion2.clkint.syn_black_box 
Post processing for smartfusion2.clkint.syn_black_box
Post processing for work.trigger_receiver_v1_7_fccc_1_fccc.def_arch
@N:CD630 : Trigger_receiver_v1_7_FCCC_0_FCCC.vhd(8) | Synthesizing work.trigger_receiver_v1_7_fccc_0_fccc.def_arch 
Post processing for work.trigger_receiver_v1_7_fccc_0_fccc.def_arch
@N:CD630 : Daq_header_read.vhd(23) | Synthesizing work.daq_header_read.behave 
Post processing for work.daq_header_read.behave
@N:CD630 : coreapb3.vhd(14) | Synthesizing coreapb3_lib.coreapb3.capb3ioi 
@W:CD604 : coreapb3.vhd(440) | OTHERS clause is not synthesized 
@W:CD638 : coreapb3.vhd(364) | Signal capb3olil is undriven 
@N:CD630 : coreapb3_muxptob3.vhd(14) | Synthesizing coreapb3_lib.capb3il.capb3o0 
Post processing for coreapb3_lib.capb3il.capb3o0
Post processing for coreapb3_lib.coreapb3.capb3ioi
@N:CD630 : apb_to_dcs.vhd(9) | Synthesizing work.apb_to_dcs.arc 
@N:CD233 : apb_to_dcs.vhd(53) | Using sequential encoding for type state
@W:CD604 : apb_to_dcs.vhd(133) | OTHERS clause is not synthesized 
Post processing for work.apb_to_dcs.arc
Post processing for work.trigger_receiver_v1_7.rtl
@END

At c_vhdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 105MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Oct 22 09:06:41 2013

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