@W:CD326 : trigger_receiver.vhd(306) | Port l2_extendedlatency of entity work.rcu_com_release is unconnected @W:CD638 : COREFIFO.vhd(245) | Signal cfifoo1l is undriven @W:CD638 : COREFIFO.vhd(247) | Signal cfifol1l is undriven @W:CD638 : COREFIFO.vhd(253) | Signal cfifol0l is undriven @W:CD638 : COREFIFO.vhd(259) | Signal cfifoi0l is undriven @W:CD638 : COREFIFO.vhd(285) | Signal cfifoi0i is undriven @W:CD638 : fifocore_sync_scntr.vhd(108) | Signal cfifooiil is undriven @W:CL169 : fifocore_sync_scntr.vhd(245) | Pruning register CFIFOL0il @W:CL169 : fifocore_sync_scntr.vhd(237) | Pruning register CFIFOl1OL @W:CL111 : fifocore_sync_scntr.vhd(279) | All reachable assignments to CFIFOoOLl assign '0'; register removed by optimization @W:CL111 : fifocore_sync_scntr.vhd(279) | All reachable assignments to CFIFOLOll assign '0'; register removed by optimization @W:CL111 : fifocore_sync_scntr.vhd(253) | All reachable assignments to CFIFOi1OL assign '0'; register removed by optimization @W:CL111 : fifocore_sync_scntr.vhd(253) | All reachable assignments to CFIFOO1oL assign '0'; register removed by optimization @W:CD604 : sequence_validator.vhd(253) | OTHERS clause is not synthesized @W:CD434 : sequence_validator.vhd(189) | Signal timeout_counter in the sensitivity list is not used in the process @W:CL169 : sequence_validator.vhd(261) | Pruning register timeout_counter(3 downto 0) @W:CL169 : sequence_validator.vhd(261) | Pruning register pre_pulseR @W:CL190 : sequence_validator.vhd(261) | Optimizing register bit prepulse_error to a constant 0 @W:CL169 : sequence_validator.vhd(261) | Pruning register prepulse_error @W:CD604 : serialb_com.vhd(148) | OTHERS clause is not synthesized @W:CD638 : rcu_dec.vhd(449) | Signal d_siu_rst is undriven @W:CD434 : rcu_reg.vhd(203) | Signal clk in the sensitivity list is not used in the process @W:CD434 : rcu_reg.vhd(265) | Signal rst in the sensitivity list is not used in the process @W:CL117 : rcu_reg.vhd(205) | Latch generated from process for signal st_meb_full; possible missing assignment in an if or case statement. @W:CD604 : arbit.vhd(110) | OTHERS clause is not synthesized @W:CD604 : arbit.vhd(139) | OTHERS clause is not synthesized @W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal siu_dout(31 downto 0); possible missing assignment in an if or case statement. @W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal rcu_data(31 downto 0); possible missing assignment in an if or case statement. @W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal dcs_dout(31 downto 0); possible missing assignment in an if or case statement. @W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal rcu_add(15 downto 0); possible missing assignment in an if or case statement. @W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal rcu_we; possible missing assignment in an if or case statement. @W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(16) | XTLOSC_O2F is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(15) | XTLOSC_CCC is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(14) | RCOSC_1MHZ_O2F is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(13) | RCOSC_1MHZ_CCC is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(12) | RCOSC_25_50MHZ_O2F is not assigned a value (floating) -- simulation mismatch possible. @W:CD604 : coreapb3.vhd(440) | OTHERS clause is not synthesized @W:CD638 : coreapb3.vhd(364) | Signal capb3olil is undriven @W:CD604 : apb_to_dcs.vhd(131) | OTHERS clause is not synthesized @W:CL246 : apb_to_dcs.vhd(21) | Input port bits 31 to 20 of paddr(31 downto 0) are unused @W:CL159 : coreapb3.vhd(50) | Input iaddR is unused @W:CL159 : coreapb3.vhd(51) | Input PRESetn is unused @W:CL159 : coreapb3.vhd(52) | Input PCLK is unused @W:CL159 : coreapb3.vhd(82) | Input prdataS0 is unused @W:CL159 : coreapb3.vhd(83) | Input PRdatas1 is unused @W:CL159 : coreapb3.vhd(84) | Input Prdatas2 is unused @W:CL159 : coreapb3.vhd(85) | Input prdatAS3 is unused @W:CL159 : coreapb3.vhd(86) | Input PRDATAS4 is unused @W:CL159 : coreapb3.vhd(88) | Input prdataS6 is unused @W:CL159 : coreapb3.vhd(89) | Input PRDATAs7 is unused @W:CL159 : coreapb3.vhd(91) | Input PRDATas9 is unused @W:CL159 : coreapb3.vhd(92) | Input PRDATAs10 is unused @W:CL159 : coreapb3.vhd(93) | Input PRdatas11 is unused @W:CL159 : coreapb3.vhd(94) | Input PRDATas12 is unused @W:CL159 : coreapb3.vhd(95) | Input PRDatas13 is unused @W:CL159 : coreapb3.vhd(96) | Input PRDATAS14 is unused @W:CL159 : coreapb3.vhd(97) | Input PRDATAS15 is unused @W:CL159 : coreapb3.vhd(99) | Input PREadys0 is unused @W:CL159 : coreapb3.vhd(100) | Input preadys1 is unused @W:CL159 : coreapb3.vhd(101) | Input preadys2 is unused @W:CL159 : coreapb3.vhd(102) | Input preadys3 is unused @W:CL159 : coreapb3.vhd(103) | Input PREADYS4 is unused @W:CL159 : coreapb3.vhd(105) | Input preadys6 is unused @W:CL159 : coreapb3.vhd(106) | Input preadys7 is unused @W:CL159 : coreapb3.vhd(108) | Input PReadys9 is unused @W:CL159 : coreapb3.vhd(109) | Input preadys10 is unused @W:CL159 : coreapb3.vhd(110) | Input PREADYS11 is unused @W:CL159 : coreapb3.vhd(111) | Input pREADYS12 is unused @W:CL159 : coreapb3.vhd(112) | Input preadyS13 is unused @W:CL159 : coreapb3.vhd(113) | Input PREAdys14 is unused @W:CL159 : coreapb3.vhd(114) | Input Preadys15 is unused @W:CL159 : coreapb3.vhd(116) | Input PSLVerrs0 is unused @W:CL159 : coreapb3.vhd(117) | Input pslverrs1 is unused @W:CL159 : coreapb3.vhd(118) | Input PSlverrs2 is unused @W:CL159 : coreapb3.vhd(119) | Input PSLVERRS3 is unused @W:CL159 : coreapb3.vhd(120) | Input pslverRS4 is unused @W:CL159 : coreapb3.vhd(122) | Input PSLVERRS6 is unused @W:CL159 : coreapb3.vhd(123) | Input Pslverrs7 is unused @W:CL159 : coreapb3.vhd(125) | Input pslVERRS9 is unused @W:CL159 : coreapb3.vhd(126) | Input PSLVERrs10 is unused @W:CL159 : coreapb3.vhd(127) | Input PSLverrs11 is unused @W:CL159 : coreapb3.vhd(128) | Input PSLVERRS12 is unused @W:CL159 : coreapb3.vhd(129) | Input pslverrs13 is unused @W:CL159 : coreapb3.vhd(130) | Input Pslverrs14 is unused @W:CL159 : coreapb3.vhd(131) | Input pslverRS15 is unused @W:CL159 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(10) | Input XTL is unused @W:CL159 : rcu_dec.vhd(197) | Input fsmrd_st_a is unused @W:CL159 : rcu_dec.vhd(198) | Input fsmwr_st_b is unused @W:CL246 : broadcast_msg_decoder.vhd(45) | Input port bits 7 to 3 of brcdata(7 downto 0) are unused @W:CL159 : sequence_validator.vhd(46) | Input pre_pulse is unused @W:CL159 : sequence_validator.vhd(71) | Input L1_msg_tw_passed is unused @W:CL159 : ms_event_fifo_ms_event_fifo_0_ram_wrapper.vhd(27) | Input RCLOCK is unused @W:CL159 : ms_event_fifo_ms_event_fifo_0_ram_wrapper.vhd(28) | Input WCLOCK is unused @W:CL159 : COREFIFO.vhd(62) | Input MEmrD is unused